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copyright ? cirrus logic, inc. 2012?2015 (all rights reserved) http://www.cirrus.com ds963f5 aug ?15 boosted class d amplifier with speaker-protection monitoring and flash led drivers mono class d speaker amplifier ? two-level class g operation: ? boosted: 5 v nominal ? bypassed: battery voltage is supplied directly ? 2.5-ma quiescent current, monitors powered down ? 1.7 w into 8 ?? (@ 10% thd+n) ? 102-db signal-to-noise ratio (snr, a-weighted) ? idle channel noise 25 ? vrms (a-weighted) ? 90% efficiency audio input and gain ? one differential analog input ? speaker gain: ? 9, 12, 15, and 18 db and mute ? pop suppression, zero-c rossing detect transitions flash led drivers ? integrated dual led drivers using the following: ? boost supply output voltage ? dual matched current regulators, 750 ma max each ? programmable setting for flash mode current: 50?750 ma, in 50-ma steps ? programmable setting for flash-inhibit mode current: 50?350 ma, in 50-ma steps ? programmable setting for movie mode current: 150, 120, 100, 80, 60, 40, 20 ma ? programmable flash timer setting: 50?500 ms, in 25-ms steps ? dedicated pin for flash trigger (flen) ? dedicated pin for flash inhibit (flinh) ? thermally managed through boost-voltage regulation ( features continue on page 2) class d power stage spkr supply vp gndpled current mode synchronous boost controller vcom range scaling class d front end short circuit protection ? class d modulator v ref generation bandgap voltage generation filt+ vref isense+ isense?/ vsense+ gnda sclk lrck soft ramp level shifters i2c control port sda scl sclk lrck sdout mclk in? ? + 9 ,12 ,15 , or 18 db + mute in+ flash led current driver control, sensing, and fault protection flout1 flout2/ad0 flen flinh spkout+ spkout?/ vsense? i 2 c class g override watchdog error gndp vsense? vsense+ isense? isense+ spkr supply ?? adc serial audio/data port serial port clock generation va reset int vmon adc front end lp imon adc front end lp low battery management class g vbst current sense iref+ sw power budgeting temperature sensor overtemp protection ?? adc ?? adc CS35L32
2 ds963f5 CS35L32 general description the CS35L32 is a low-quiescent power-integrated audio ic, with a mono full-bridge class d speaker amplifier operating with a self-boosted class g supply. audio input is received differentially. pop-and-click reduction is achieved with zero- crossing transitions at turn-on, turn-off and upon gain chang es. communication with the host processor is done using an i 2 c interface. in addition, an i 2 s bus is used to send monitor and status data. when two CS35L32 devices are available on the same board, each is identified by its i 2 c chip address. upon power-up or upon deasserting reset , each CS35L32 reads the ad0 pin logic level and configures its i 2 c device address. the speaker amplifier, using closed-loop ?? modulation, achieves low levels of di stortion. class d amplifier efficiency allows operation at higher speaker power levels without gene rating excessive heat and without wasting power. automatic class g operation using a boosted supply to the speaker allows for even higher powers and higher crest factor. with a boosted speaker supply, operation at a fixed 5 v is achieved independently of line supplied ba ttery voltage. the user can disable class g operation. monitors and protection ?protection: ? latched overtemperature shutdown ? latched amplifier output short circuit shutdown ? led short or open detection and led driver shutdown ? flash inhibit led current reduction ? low battery flash led current reduction ? vp undervoltage lockout (uvlo) shutdown ? programmable boost inductor current limiting ? audio and led shutdown upon stopped mclk, with autorecovery ? interrupt driven error reporting ? speaker current and voltage monitoring: ? 16-bit resolution ? 60-db dynamic range (unweighted) for voltage ? 56-db dynamic range (unweighted) for current ? bused over i 2 s bus ? battery voltage monitoring: ? 7-bit resolution ? bused over i 2 s and i 2 c bus ? system reset i 2 c control settings and registers ? low-power standby ? led and audio power budgeting programmable settings ? boost inductor current limit programmable setting ? speaker programmable settings: ? pop suppression through zero-crossing transitions ? gain and mute ? battery voltage monitor register, 8 bits ? led driver programmable settings: ? flash current register ? flash inhibit current register ? movie mode current register ? flash timer register ? error status bit, including the following: ? stopped mclk error ? low battery detection with programmable thresholds ? vp uvlo error ? overtemperature warning ? overtemperature error ? boost converter overvoltage error ? boost inductor curr ent-limiting error ? amplifier short-circuit error ? shorted or open led error i 2 s reporting ? monitoring: ? speaker voltage monitor ? speaker current monitor ? battery voltage monitor ? error reporting: ? vp uvlo shutdown error ? overtemperature warning ? overtemperature error ? boost converter overvoltage error ? boost inductor curr ent limiting error ? amplifier short-circuit error ? speaker voltage monitor overflow error ? speaker current monitor overflow error ? battery voltage monitor overflow error ? status reporting: ? power-down done ? led flash event ? led movie mode event ? flash timer on package ? 30-ball wlcsp applications ? smart phones ?tablets
ds963f5 3 CS35L32 the battery voltage, speaker voltage, and speake r current signals are moni tored, digitized using ?? converters, and serialized over an i 2 s bus. the speaker monitoring signals are part of a speaker-protection al gorithm that is managed externally to the CS35L32. ou tgoing data is sent over i 2 s with the CS35L32 in slave or master mode. battery voltage monitor data is accessible through i 2 c. an integrated dual led driver operates up to two leds in flash mode or movie mode. a flash event is triggered by an external signal. a flash-inhibit event is triggered by an extern al signal, and causes a reduction in flash current. a timer is provided for flash and flash inhibit events. movie mode operation has no timer and starts and ends via an i 2 c command. flash and movie mode current levels, as well as the flash timer are i 2 c programmable. total power consumption when powering leds in flash mo de or movie mode, and powering audio simultaneously, is managed by the user?s choices in programming the current limit and in power budgeting. the primary goal is to manage audio and led loads so the boost converter is not current limited and so the CS35L32 does not shut down due to overheating. a latched shutdown of the audio amplifier occurs in the event of an output short pin to ground, pin to supply, or pin to pin. a latched shutdown of the CS35L32 also occurs on overtemperature. an led driver shutdown occurs in the event of a shorted or open led. the CS35L32 shuts down in the event of a battery (vp) undervoltage and autorecovers when the battery voltage recovers. the CS35L32 shuts down in the event of a stopped mclk and autorecovers when mclk recovers. the CS35L32 responds to detection of a low battery in the presence of a flash event by reducing flash current and autorecovers when the battery voltage recovers. the CS35L32 is rese t by asserting reset . CS35L32 power up and power down are man aged through the reset pin. the CS35L32 is available in a 30-ball wlcsp package in the temperature range ?10 to +70c.
4 ds963f5 CS35L32 table of contents 1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 typical connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 characteristics and specifications . . . . . . . . . . . . . . . . . . . . . . 8 table 3-1. recommended operating conditions . . . . . . . . . . . . . . . . . . 8 table 3-2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3-3. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3-4. boost converter characteristics . . . . . . . . . . . . . . . . . . . . . . 9 table 3-5. led drive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3-6. speaker amplifier output characteristics . . . . . . . . . . . . . . 10 table 3-7. signal monitoring characteristics . . . . . . . . . . . . . . . . . . . . 11 table 3-8. digital interface specifications and characteristics . . . . . . . 11 table 3-9. psrr characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3-10. power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3-11. switching specifications: po wer, reset, master clocks . . 12 table 3-12. switching s pecifications: adsp in i 2 s mode . . . . . . . . . . . 13 table 3-13. switching specifications: i2c control port . . . . . . . . . . . . . 14 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 speaker amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 low-battery management . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 undervoltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7 die temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.8 signal monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.9 led driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.10 power budgeting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.11 audio/data serial port (adsp) . . . . . . . . . . . . . . . . . . . . . . 24 4.12 signaling format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.13 device clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.14 control port operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 required reserved register configuration . . . . . . . . . . . . . 32 5.2 avoiding current transients when issuing a flash event . . 32 5.3 external component and pcb design considerations?emi out- put filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4 pcb routing considerations for thermal relief . . . . . . . . . 33 5.5 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 register quick reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 device id a and b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 device id c and d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 device id e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4 revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5 power control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.6 power control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.7 clocking control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.8 low battery thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.9 battery voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.10 boost converter peak current protection control . . . . . . . 38 7.11 scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.12 led and audio power-budget management . . . . . . . . . . . 38 7.13 adsp control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.14 class d amplifier control . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.15 protection release control . . . . . . . . . . . . . . . . . . . . . . . . 39 7.16 interrupt mask 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.17 interrupt mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.18 interrupt mask 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.19 interrupt status 1 (audio) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.20 interrupt status 2 (monitors) . . . . . . . . . . . . . . . . . . . . . . . . 42 7.21 interrupt status 3 (leds and boost converter) . . . . . . . . . 42 7.22 led lighting status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.23 led flash mode current . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.24 led movie mode current . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.25 led flash timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.26 led flash inhibit current . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 typical performance plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.1 system-level efficiency and power-consumption plots . . . 45 8.2 audio output typical performance plots . . . . . . . . . . . . . . . 46 8.3 monitoring typical performance plots . . . . . . . . . . . . . . . . . 47 9 parameter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ds963f5 5 CS35L32 1 pin descriptions 1 pin descriptions figure 1-1. top-down (through-package) view?30-ball wlcsp package ??? ? ? sda scl sdout sclk mclk flout2/ ad0 ????? vp int reset lrck gndpled flout1 ????? sw gndp gndp flinh gnda va ????? sw spkout+ spkout?/ vsense? flen iref+ filt+ ????? vbst spkrsupply in? in+ isense?/ vsense+ isense+ table 1-1. pin descriptions ball name ball number power supply i/o ball description internal connection driver receiver state at reset sda a1 va i/o i 2 c serial data input. serial data for the i 2 c serial port ?cmos open-drain output hysteresis on cmos input hi-z scl a2 va i i 2 c clock input. serial clock for the i 2 c serial port ??hysteresis on cmos input hi-z mclk a5 va i master clock source. clock source for a/d converters and audio/data serial port (adsp). mclk int , derived from mclk, is used for other blocks (see section 4.13 and section 7.7 ). weak pull- down (~1 m ?? ? hysteresis on cmos input pulled down sclk a4 va i/o serial clock. serial shift clock for the serial audio interface weak pull- down (~1 m ?? cmos output hysteresis on cmos input pulled down lrck b4 va i/o left right clock. determines which channel, left or right, is currently active on the serial audio/data lines weak pull- down (~1 m ?? cmos output hysteresis on cmos input pulled down sdout a3 va o serial audio/data output. i2s serial data output used to monitor voltage and current of spkout signal and vp levels weak pull-down (~1 m ?? cmos output ? pulled down int b2 va o interrupt. programmable, open-drain, active- low programmable interrupt output ?cmos open-drain output ?hi-z a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 c1 c2 c3 c4 c5 c6 d1 d2 d3 d4 d5 d6 e1 e2 e3 e4 e5 e6 general ground led digital i/o power supply boost converter audio digital i/o
6 ds963f5 CS35L32 1 pin descriptions reset b3 va i reset. when asserted, the device enters a low-power mode, outputs are set to hi-z, and i2c register values are set to defaults. outputs are hi-z except those with weak pull-ups or pull-downs as mentioned. ? ? hysteresis on cmos input low flen d4 va i flash enable. input signal commanding a flash event into both leds. it is asserted high. weak pull- down (~1 m ?? ? hysteresis on cmos input pulled down flinh c4 va i flash inhibit. input signal determining whether the leds are in flash mode (logic low) or flash-inhibit mode (logic high, led current reduced). weak pull- down (~1 m ?? ? hysteresis on cmos input pulled down flout1 b6 spkr supply o led driver 1. output driving led 1 by sinking current from the led cathode weak pull-up (~1 m ?? ? ? spkr supply flout2/ad0 a6 spkr supply i/o led driver 2/address zero. output driving led 2 by sinking current from the led cathode. ad0 programs the chip address when reset is deasserted. if no led is used, tying the pin to ground clears the chip address lsb. otherwise, the lsb is set. weak pull-up (~1 m ?? ? ? spkr supply vbst e1 ? o boost converter output. output of boosted supply. this pin cannot be used to drive any external loads other than the on chip class d amplifier and flash leds. ???? spkrsupply e2 ? i speaker supply. full-bridge class d speaker amplifier power supply. ?? sw c1, d1 vbst i boost converter switch node. connects the inductor to the rectifying switch. ???? iref+ d5 va i current reference resistor. connection for an external resistor to be used for generating the CS35L32?s internal main current reference. see fig. 2-1 for required resistor value. ???? in+ e4 spkr supply i input 1 differential positive line. positive analog input ???? in? e3 spkr supply i input 1 differential negative line. negative analog input ???? spkout+ spkout?/vsense? d2 d3 spkr supply o speaker differential audio output. internal class d speaker amplifier output. spkout? serves as voltage monitor negative sense pin (vsense?). ???hi-z isense+ isense?/vsense+ e6 e5 spkr supply i current sense inputs. sense voltage across an external resistor in series with spkout+. isense? serves as voltage monitor positive sense pin (vsense+). ???? filt+ d6 va o positive voltage reference. positive reference for internal circuits ???? va c6 ? i analog input power. power supply for internal analog section ???? vp b1 ? i boost converter input power. power supply or battery voltage powering boost converter ???? gnda c5 ? analog ground. ground reference for the internal analog section of the ic ???? gndp c2, c3 ? power ground. ground reference for boost converter and class d amplifier?s output stage ???? gndpled b5 ? led power ground. ground reference for led current return. should be tied to ground plane. ???? table 1-1. pin descriptions (cont.) ball name ball number power supply i/o ball description internal connection driver receiver state at reset led boost converter audio power supply general ground
ds963f5 7 CS35L32 2 typical connection diagram 2 typical connection diagram figure 2-1. typical connection diagram battery 1 ? h c out 0.1 ? 0.1 ? f ** l bst 44.2 k ? r bst_sns 8 ? c out ** applications processor 0.1 ? f 10 ? f c bst * * r p r p r p _ i pmu 10 ? f * 0.1 ? f va * 4.7 ? f * line input 1 CS35L32 isense?/ vsense+ spkout+ isense+ iref+ spkout?/ vsense? vbst gndp flout1 flout2 / ad0 gndpled spkrsupply sdout lrck sclk mclk flen flinh scl sda int reset va filt+ gnda in+ in? vp sw * * 3.0?5.25 v 1.71?1.89 v 10 ? f notes: ? all external passive component values are nominal values. key for capacitor types required: * use low esr, x7r/x5r capacitors. ** use low esr, x7r capacitors. if no type symbol is shown next to a capacitor, any type may be used. ? as required, add protection circuitry to ensure compliance with the absolute maximum ratings in ta b l e 3 - 2 . 1. c bst is a ceramic capacitor and derates at dc voltages higher than 0 v. in this application, the capacitor should not derate to a v alue lower than 4 ? f across the specified boost output voltage in ta b l e 3 - 4 . capacitor tolerance and the temperature coefficient should also be taken into account to guarantee the 4- ? f value. 2. minimum pull-up resistor values are selected in accordance with the table 3-8 v ol specification . maximum pull-up resistances are selected based on load capacitance and relevant switching specs ( table 3-13 ). 3. select each capacitor to be 0.22 ? f for an 18-hz passband @ 12-db amplifier gain, for a 3-db roll-off. the equation for calculating the capacitance for a given passband is c = 1/( ? * f * r indif ), where c is in f, r indif is the differential input resistance in ??? and f is in hz (see the differential input resistance specification in ta b l e 3 - 3 ). signals in+ and in? are subject to the recommended ranges in table 3-1 . 4. r bst_sns is inherently tied to the accuracy of the bst_ipk current limit. a resistor with a 0.1% tolerance is required for this compone nt to meet the specified imax(b) max and min values in table 3-4 . 5. the required tolerance on the 0.1- ? isense resistor is 1%. the required temperature coefficient is 200 ppm/c. 6. c out capacitors are optional emi suppressors used with CS35L32 edge- rate control, depending on application requirements. because switching losses increase linearly with increases to these capacitances, it is recommended that c out values not exceed 2 nf. the recommended value is 470 pf. 7. led and i 2 c addressing options: vbst vbst c) ad0 = 1 d) ad0 = 0 b) ad0 = 1 a) ad0 = 1 vbst vbst flout1 flout2 flout1 flout2 flout1 flout2 flout1 flout2 nc see note 7 for led and i 2 c addressing options. note 1 note 3 note 2 note 5 note 4 note 6
8 ds963f5 CS35L32 3 characteristics and specifications 3 characteristics and specifications table 3-1. recommended operating conditions gnda = gndp = 0 v, all voltages with respect to ground. device functional opera tion is guaranteed within these limits. functiona lity is not guaranteed or implied outside of these limits. o peration outside of these limits may adversely affect device reliability. parameters symbol minimum maximum units dc power supply analog (and digital i/o and core) va 1.71 1.89 v battery vp 3.0 5.25 v external voltage applied to analog inputs powered by va (iref+, filt+) 1 1.the maximum overvoltage/undervoltage is limited by the input current. v inas ?0.3 va + 0.3 v external voltage applied to analog inputs powered by spkrsupply (in+, in?, isense+, isense?,vsense+, vsense?) v inss ?0.3 spkrsupply + 0.3 v external voltage applied to digital inputs v indi ?0.3 va + 0.3 v ambient temperature ta ?10 +70 c table 3-2. absolute maximum ratings gnda = gndp = 0 v; all voltages with res pect to ground. operation at or beyond thes e limits may permanently damage the device. parameters symbol minimum maximum units dc power supply analog va ?0.3 2.22 v battery vp ?0.3 6.0 v input current 1 1. any pin except supplies. transient currents of up to 100 ma on the analog input pins do not cause scr latch up. i in ?10ma ambient operating temperature (local to device, power applied) t a ?40 +115 c junction operating temperature (power applied) t j ?40 +150 c storage temperature t stg ?65 +150 c table 3-3. dc characteristics test conditions, except where noted otherwise: va = 1.8 v, vp = 3.6 v, vbst = 5.0 v, gnda = gndp = 0 v, ta = +25c . parameters symbol test conditions min typical max units differential input resistance (in+ to in?) r indif amp gain = 9 db amp gain = 12 db amp gain = 15 db amp gain = 18 db ? ? ? ? 63 51 40 31 ? ? ? ? k ? k ? k ? k ? filt+ voltage ? ? ? va ? ? overtemperature shutdown threshold t op ? ? 150 ? c overtemperature warning threshold t wrn ? ? 135 ? c overtemperature warning threshold deviation ? ? ? 10 ? c low battery threshold ? lowbat_th = 00 lowbat_th = 01 lowbat_th = 10 lowbat_th = 11 ? ? ? ? 3.10 3.20 3.30 3.40 ? ? ? ? v v v v low-battery recovery threshold ? lowbat_recov = 001 lowbat_recov = 010 lowbat_recov = 011 lowbat_recov = 100 lowbat_recov = 101?11x ? ? ? ? ? 3.20 3.30 3.40 3.50 3.60 ? ? ? ? ? v v v v v vp undervoltage lockout threshold (vp falling) uvlo ? ? 2 ? v vp undervoltage lockout hysteresis ? ? ? 100 ? mv
ds963f5 9 CS35L32 3 characteristics and specifications table 3-4. boost converter characteristics test conditions, except where noted otherwise: va = 1.8 v, vp = 3.6 v, vbst = 5.0 v, amp gain = 12 db, gnda = gndp = 0 v, ta = +25c , mclk int = 6 mhz. mclk int is explained in section 4.13.1 and section 7.7 . parameters symbol test conditions min typical max units boost output voltage vbst boosting bypass vp*1.15 ? ? vp 5.4 ? v v boost output voltage tolerance ? vbst no load: i load =0 ma ?5 ? +5 % load regulation ? v (load) 3.0 v < vp < 4.2 v; i load = 0.25a to1.5 a ? 60 ? mv/a line regulation ? v (line) 3.0 v 10 ds963f5 CS35L32 3 characteristics and specifications table 3-6. speaker amplifier output characteristics test conditions, except where noted otherwise: va = 1.8 v, vp = 3.6 v, vbst = 5.0 v, 1-khz input, amp gain = 12 db, gnda = gndp = 0 v, t a = +25c, measurement bandwidth is 20 hz to 20 khz, fs = 48 khz, mclk int = 6 mhz. mclk int is explained in section 4.13.1 and section 7.7 . parameters symbol test conditions min typical max units continuous average power delivered to load 1 1.power delivered to the speaker from the 0.1- ? load side terminal (refer to fig. 2-1 ). po 8- ? load, thd 10% 8- ? load, thd 1% ? ? 1.75 1.45 ? ? w w thd+n thd+n 8- ? load, 1.0 w ? 0.02 ? % input voltage @ 1% thd+n v iclip 8- ? load ? 0.84 ? vrms signal to noise ratio snr referenced to output voltage @1% thd+n, a-weighted ? 102 ? db idle channel noise icn vbst = vp, a-weighted ? 25 ? ? vrms common-mode rejection ratio cmrr v ripple = 1 v pp , f ripple = 217 hz ? 55 ? db frequency response fr 20 hz to 20 khz, no input dc blocking caps ?0.1 0 0.1 db efficiency 2 2.efficiency collected using a 5-v external supply, as shown in the drawing. for this test, the vbst pin should not be connected to the spkrsupply pin. ? a 8- ? load 33 ? h, 1.7 w ? 91 ? % class d amplifier gain ? amp_gain = 000 (mute) amp_gain = 001 amp_gain = 010 amp_gain = 011 amp_gain = 100 ? ? ? ? ? ?80 9 12 15 18 ? ? ? ? ? db db db db db n-fet on resistance r ds on,n i fet = 0.5 a ? 185 ? m ? p-fet on resistance r ds on,p i fet = 0.5 a ? 205 ? m ? output dc offset voltage v offset inputs ac coupled to ground ? 5 ? mv time from shutdown to audio out t sd reset deasserted, zero-crossing disabled ? 15 ? ms generic simulated speaker load r sense 0.1 ? audio precision ap 2700 audio analyzer audio precision aux-0025 filter spkout+ isense+ spkout? isense?/ vsense+ vsense? spkrsupply 5 v 3.6 v 1.8 v vp va 8 ? 33 ? h
ds963f5 11 CS35L32 3 characteristics and specifications table 3-7. signal monitoring characteristics test conditions, except where noted otherwise: va = 1.8 v, vp = 3.6 v, vbst = 5.0 v, amp gain = 12 db, 0.1- ? sense resistor, gnda = gndp = 0 v, t a = +25c. measurement bandwidth is 20 hz to 20 khz, fs = 48 khz, input signal = 1 khz, mclk int = 6 mhz, mclk int is explained in section 4.13.1 and section 7.7 . parameters min typical max units general adc characteristics power-up time: t pup(adc) ?8.5 [1] 1.typical value is specified with pdn_amp and pdn_xmon bits initially set. maximum pow er-up time is affected by the actual mclk int frequency. ms vsense monitoring characteristics (vmon) data width ? 16 ? bits dynamic range (unweighted), vsense = 5.0 v (10 v pp )? 60 ? db 2 2.parameters given in db are referred to the applicable typica l full-scale voltages. applies to all thd+n and resolution values in the table total harmonic distortion + noise, ?3.8 dbfs 3 3.vsense thd is measured with the class d amplifier as the audio source connected to an 8- ? + 33 ? h speaker load, supplied by a 6.3-v pp , 1-khz sine wave, operating under the typical perfo rmance test conditions to produce a lar ge, unclipped audio signal. this setup produ ces a ?3.8-dbfs vmon output. larger class d amplifier amplitudes begin to exhibi t clipping behavior, increasing distortion of the signal suppli ed to vsense ? ?60 ? db 2 full-scale signal input voltage 6.59?va 6.94?va 7.29?va v pp common-mode rejection ratio (217 hz @ 500 mv pp ) 4 4.cmrr test setup for vsense: ?60?db 2 group delay 5 5.vmon group delay is measured from the time a signal is pres ented on the vsense and pins until the msb of the digitized signa l exits the serial port. fs is the lrck rate. ?7.6/fs? s isense monitoring characteristics (imon) data width ? 16 ? bits dynamic range (unweighted), isense = 0.625 a (1.25 a pp )? 56 ? db 2 total harmonic distortion, ?29.5 dbfs 6 6.for reference, injecting a 125-mvpp fully differential sine wave into the isense pins (equivalent to a 0.625 a current with a 0.1- ? isense resistor) produces an imon output of ?29.5 dbfs (since typical full-scale is 1.64*va, in v pp ). isense monitoring thd is measured using the class d amplifier as the audio source, which is connected to an 8- ? + 33- ? h speaker load, supplied by a 7.0-v pp , 1-khz sine wave, operating under the typical performance test conditions to produce a large, uncli pped audio signal. this setup produces a ?29.5-dbfs amplitude imon output. larger class d amplifier amplitudes begin to ex hibit clipping behavior, increasing the dist ortion of the signal supplied to isense. ? ?45 ? db 2 full-scale signal input voltage 1.56?va 1.64?va 1.72?va v pp vmon-to-imon isolation 7 7. vmon-to-imon isolation is the error in the current sense due to vmon, expre ssed relative to full-scale sense current in decibels. ?56?db 2 group delay 8 8.imon group delay is measured from when a signal is presented on the isense pins unt il the msb of the digitized signal exits the serial port. fs is the lrck rate. ?7.6/fs? s vp monitoring characteristics data width ? 8 ? bits voltage resolution (see the equation in section 4.8.4 .) ? 35.3 ? mv (ff code) signal input voltage (vp) 2.89?va 3.05?va 3.20?va v vpmon = 1011 0011 vpmon = 1011 0100 ? vpmon = 1111 1111 vpmon = 0000 0000 ? ? ? ? ? 2.8 2.835 ? 5.482 5.518 ? ? ? ? ? v v ? v v table 3-8. digital interface spec ifications and characteristics test conditions, except where noted otherwise: va = 1.8 v, vp = 3.6 v, vbst = 5.0 v, gnda = gndp = 0 v, t a = +25c. parameters symbol test conditions min max units input leakage current (per pin) 1,2 1.specification includes current through internal pull up/down resistors, where applicable (as defined in section 1 ). 2.leakage current is measured with va = 1.80 v, vp = 3.60 v, vbst = 3.60 v, and reset asserted. each pin is tested while driven high and low. flout2/ad0 flen, flinh, lrck mclk, sclk, sdout scl , sda, int , reset i in ? ? ? ? ? ? ? ? 7.5 4.5 4.5 0.1 ? a ? a ? a ? a input capacitance i in ? ? 10 pf va logic i/os high-level output voltage v oh i oh = ?67/?100 ? a 3 3.for the adsp output sdout and potential outputs sclk and lrck (if m/s = 1), if adsp_drive = 0 see section 7.13 , i oh and i ol are ?100 and +100 ? a. if adsp_drive = 1, i oh and i ol are ?67 and +67 ? a. for other, non-adsp_drive-affected outputs, i oh and i ol are ?100 and +100 ? a. va?0.2 ? v low-level output voltage v ol all outputs, i ol = 67/100 ? a 3 int , sda, i ol = 3 ma ? ? 0.20 0.4 v v high-level input voltage v ih ?0.70?va ? v low-level input voltage v il ? ? 0.30?va v vsense+ 217 hz 500 mv pp dc offset = 0 vsense?
12 ds963f5 CS35L32 3 characteristics and specifications table 3-9. psrr characteristics test conditions, except where noted otherwise: va = 1.8 v, vp = 3.6 v, vbst = vp, amp gain = 12 db, gnda = gndp = 0 v, t a = +25c. parameters conditions noise injected into noise measured on noise amplitude (mv) noise frequency (hz) min typical max units speaker amplifier psrr vbst = vp va spkout 100 217 1k 20k ? ? ? 75 75 70 ? ? ? db db db vp spkout 100 217 1k 20k ? ? ? 70 70 55 ? ? ? db db db vpmon psrr vbst = vp va sdout 100 217 1k 20k ? ? ? 36 36 33 ? ? ? db db db vsense psrr 1 1.the speaker voltage monitor has a lower psrr because its input path has an attenuation of 16.6 db. the psrr specification is referred to the input signal and, as such, includes the loss of 16.6 db. vbst = vp va sdout 100 217 1k 20k ? ? ? 60 60 50 ? ? ? db db db isense psrr vbst = vp va sdout 100 217 1k 20k ? ? ? 60 60 60 ? ? ? db db db table 3-10. power consumption test conditions, except where noted otherwise: va = 1.8 v, vp = 3.6 v, vbst = vp, gnda = gndp = 0 v, t a = +25c. use configuration typical current i vp i va units powered up ( pdn_bst = 00) reset asserted, mclk, sclk, lrck inactive 11 ? a in+ in? shorted to ground, leds off, monitors powered down 1 1.refer to section 7.6 for configuring monitor power down no c out 3270 390 ? a in+ in? shorted to ground, leds off, monitors powered down 1 c out = 470 pf (see fig. 2-1 ) 4275 390 ? a in+ in? shorted to ground, leds off, monitors powered up 1 no c out 3360 1435 ? a in+ in? shorted to ground, leds off, monitors powered up 1 c out = 470 pf see fig. 2-1 ) 4360 1435 ? a boost mode bypass ( pdn_bst = 01) . reset asserted, mclk, sclk, lrck inactive 11 ? a in+ in? shorted to ground, leds off, monitors powered down 1 no c out 1983 390 ? a in+ in? shorted to ground, leds off, monitors powered down 1 c out = 470 pf (see fig. 2-1 ) 3093 390 ? a in+ in? shorted to ground, leds off, monitors powered up 1 no c out 2074 1435 ? a in+ in? shorted to ground, leds off, monitors powered up 1 c out = 470 pf see fig. 2-1 ) 3185 1435 ? a table 3-11. switching specifications: power, reset, master clocks test conditions, except where noted otherwise: va = 1.8 v, vp = 3.6 v, vbst = 5.0 v, t a = +25c, gnda = gndp = 0 v. fig. 2-1 shows typical connections; gnda = gndp = 0 v. section 9 describes some parameters in detai l; input timings are measured at v il and v ih thresholds; output timings are measured at v ol and v oh thresholds (see table 3-8 ). parameters symbol 1 1.power and reset sequencing min max units power supplies 2 2.vp supply may be applied or removed independently of reset and the other power rails. see section 4.1 for additional details. power supply ramp up/down t pwr-rud ? 100 ms reset 2 reset low (logic 0) pulse width t rlpw 1?ms reset hold time after power supplies ramp up t rh(pwr-rh) 1?ms reset setup time before power supplies ramp down t rs(rl-pwr) 1?ms reset rising edge to control-port active t irs [3] 3.the reset rising-edge-to-control-port-active timing, t irs , is specified in table 3-13 . ?ns master clocks mclk frequency 4 4.maximum frequency for highest supported nominal rate is indicated. the supported nominal serial port sample rates are found i n section 4.11.2 . f mclk ? 12.3 mhz mclk duty cycle d mclk 45 55 % v min gnd internal supplies stable v operating t rh(pwr-rh) t irs control port active t rs(rl-pwr) reset t pwr-rud t pwr-rud t pwr- rud t pwr-rud 1 st supply up last supply up 1 st supply down last supply down
ds963f5 13 CS35L32 3 characteristics and specifications table 3-12. switching specifications: adsp in i 2 s mode test conditions, except where noted otherwise: va = 1.8 v, vp = 3.6 v, vbst = 5.0 v, t a = +25c, inputs: logic 0 = gnda = gndp = 0 v, logic 1 = va; c load = 30 pf. section 9 describes some parameters in detai l; input timings are measured at v il and v ih thresholds; output timings are measured at v ol and v oh thresholds (see table 3-8 ). parameters symbol 1 1.adsp timing in i 2 s mode min max units slave mode input sample rate (lrck) 2 2.clock rates should be stable when the CS35L32 is powered up. fs ? 49 khz lrck duty cycle ? 45 55 % sclk frequency 1/t ps ? 64?fs hz sclk duty cycle ? 45 55 % lrck setup time before sclk rising edge t ss(lk?sk) 40 ? ns lrck hold time after sclk rising edge t hs(sk?lk) 20 ? ns sdout time from sclk to data valid start 3 3.minimum data valid window, as shown in signal diagram, is (sclkperiod ? 300 + 155) ns. for sclk = 64*fs =64*48 = 3072 khz, th is is 180 ns. t datavalidstrt ? 300 ns sdout time from sclk to data valid end 3 t datavalidend 155 ? ns master mode output sample rate (lrck) 4 4.in master mode, the output sample rate follows mclk rate divided down per table 4-14 and section 7.7 . any deviation in internal mclk from the nominal supported rates is directly imparted to the output sample rate by the same factor (e.g., +100-ppm offset in the frequen cy of mclk becomes a +100-ppm offset in lrck). fs ? [4] khz lrck duty cycle ? 45 55 % sclk frequency 1/t pm ? 64?fs hz sclk duty cycle ratio = 0 ratio = 1 [5] 5.if ratio = 1, the mclk(int)-to-lrck ratio is 125. the device per iodically extends sclk high time to compensate for a fractional mclk/sclk ratio ? ? 45 33 55 67 % % lrck setup time before sclk rising edge t sm(lk?sk) 35 ? ns lrck hold time after sclk rising edge t hm(sk?lk) 20 ? ns sdout time from sclk to data valid start 3 t datavalidstrt ? 300 ns sdout time from sclk to data valid end 3 t datavalidend 155 ? ns // lrck sclk sdout t p ? note: ? = ?s? or ?m? t s ? (lk-sk) t h ? (sk-lk) t datavalidstrt t datavalidend datavalidwind
14 ds963f5 CS35L32 3 characteristics and specifications table 3-13. switching specifications: i2c control port test conditions, except where noted otherwise: va = 1.8 v, vp = 3.6 v, vbst = 5.0 v, t a = +25c, inputs: logic 0 = gnda = gndp = 0 v, logic 1 = va; sda load capacitance equal to maximum value of c b specified below; minimum sda pull-up resistance, r p(min) . 1 section 9 describes some parameters in detail. all specifications are valid for the signals at the pins of the CS35L32 with the specified load capacitan ce; input timings are measured at v il and v ih thresholds; output timings are measured at v ol and v oh thresholds (see table 3-8 ). 1.the minimum r p and r p_i values (resistors shown in fig. 2-1 ) are determined using the maximum level of va , the minimum sink current strength of their respective output, and the maximum low-level output voltage v ol (specified in table 3-8 ). the maximum r p and r p_i values may be determined by how fast their associated signals must transition (e.g., the lower the value of r p , the faster the i 2 c bus is able to operate for a given bus load capacitance). see the i2c swit ching specifications in table 3-13 and the i2c bus specification referenced in section 13 . parameter symbol 2 2.i2c control-port timing. min max units reset rising edge to start t irs 500 ? ns scl clock frequency f scl ? 400 khz start condition hold time (before first clock pulse) t hdst 0.6 ? s clock low time t low 1.3 ? s clock high time t high 0.6 ? s setup time for repeated start condition t sust 0.6 ? s sda input hold time from scl falling 3 3.data must be held long enough to bridge the transition time, t f , of scl. t hddi 00.9s sda output hold time from scl falling t hddo 0.2 0.9 s sda setup time to scl rising t sud 100 ? ns rise time of scl and sda t rc ? 300 ns fall time of scl and sda t fc ? 300 ns setup time for stop condition t susp 0.6 ? s bus free time between transmissions t buf 1.3 ? s sda bus capacitance c b ? 400 pf t buf t low stop start start stop repeated sda scl t irs reset t hddi, t hddo t sud t sust t rc t hdst t high t hdst t fc t susp
ds963f5 15 CS35L32 4 functional description 4 functional description figure 4-1. CS35L32 block diagram 4.1 power supplies the va and vp supplies are requir ed for proper operation of the CS35L32. before either su pply is powered down, reset must be as serted. reset must be held in the asserted state until a ll supplies are up and within the recommended range. timing requirement for reset during supply power up and power down is described in table 3-11 . the vbst supply is generated internally (as described in section 7.12 ) and connected to the high-power output stage of the class d amplifier through two balls: vbst and spkrsupply. by so doing, the speaker amplifier benefit s from the proximit y of the external decoupling capacitor that is co nnected to the boosted supply. 4.2 interrupts events that require special attention, such as when a thresh old is exceeded or an error occurs, are reported through the assertion of the interr upt output pin, int . these events are captured within the interrupt status registers. events can be individually masked by setting correspondin g bits in the interrupt mask registers. table 4-1 lists interrupt status and mask registers. the configuration of mask bits determines which events cause the immediate assertion of int : ? when an unmasked interrupt status event is detected, the status bit is set and int is asserted. ? when a masked interrupt status event is detecte d, the interrupt status bit is set, but int is not affected. once int is asserted, it remains asserted until all unmasked status bits that are set have been read. interrupt status bits are sticky and read-to- clear: once set, they remain set until the register is read and the associated interrupt co ndition is not present. if a condition is still present and the status bit is read, although int is deasserted, the status bit remains set. class d power stage spkr supply vp gndpled current mode synchronous boost controller vcom range scaling class d front end short circuit protection ? class d modulator v ref generation bandgap voltage generation filt+ vref isense+ isense?/ vsense+ gnda sclk lrck soft ramp level shifters i2c control port sda scl sclk lrck sdout mclk in? ? + 9 ,12,15, or 18 db + mute in+ flash led current driver control, sensing, and fault protection flout1 flout2/ad0 flen flinh spkout+ spkout?/ vsense? i 2 c class g override watchdog error gndp vsense? vsense+ isense? isense+ spkr supply ?? adc serial audio /data port serial port clock generation va reset int vmon adc front end lp imon adc front end lp low battery management class g vbst current sense iref+ sw power budgeting temperature sensor overtemp protection ?? adc ?? adc see section 4.9 ? led driver .? see section 4.4 . see section 4.11 ? audio/data serial port (adsp) .? see section 4.8 , ? signal monitoring .? see section 4.10 , ? power budgeting .? see section 4.7 . see section 4.3 . see section 4.6 ? boost converter .? see section 4.11 . see section 4.14 . see section 4.2 . see section 4.13 , ? device clocking .?
16 ds963f5 CS35L32 4.3 speaker amplifier to clear any status bits set due to the in itiation of a path or block, all interrupt status bits should be read after reset and before normal operation begins. otherwise, unmask ing these previously set status bits causes int to assert. 4.3 speaker amplifier the CS35L32 features a high-efficiency mono class d audio amplifier, shown in fig. 4-2 , with an advanced closed-loop architecture that achieves low levels of output distortion. automatic class g ope ration, using a boosted supply to the amplifier, allows louder speaker performance with high crest factor. figure 4-2. speaker am plifier block diagram 4.3.1 class g operati on with leds off the boost converter output is the supply to the speaker amplif ier. audio operation can be programmed to have one of the following supply modes (see section 7.12 for programming details.): ? class g where the boost converter is in bypass mode for audio input signals below a threshold v in1thon and in 5-v boost mode for audio signal inputs above a threshold v in1thoff . these thresholds are specified in table 3-4 for the given conditions. the corres ponding equations are shown below. ? class g disabled, boost converter is in bypass mode, and vbst = vp. in this mode, thresholds are ignored. ? class g disabled, boost converter is in boost mode, and vbst = 5 v. in this mode, thresholds are ignored. the class g equations for the audio input signal thresholds are as follows: vbst is the boost converter output voltag e (whether in bypass or boost mode), and gain is audio gain expressed as a unitless real ratio (nonlogarithmic). k = 1 if mclk is 6 or 12 mhz; k = 1.024 if mclk is 6.144 or 12.288 mhz. mclk int should be configured as described in section 4.13.1 and section 7.7 . table 4-1. interrupt status registers and corresponding mask registers status registers mask registers interrupt status 1 (audio) ( section 7.19 ) interrupt status 2 (monitors) ( section 7.20 ) interrupt status 3 (leds and boost converter) ( section 7.21 ) interrupt mask 1 ( section 7.16 ) interrupt mask 2 ( section 7.17 ) interrupt mask 3 ( section 7.18 ) and hybrid class d audio amplifier (pdn_amp = 0) hybrid class d modulator ?? -class d modulator 9?18 db short circuit protection spkout+ spkout? hybrid class d power stage vbst in+ in? amp_gain p. 39 gain_chg_zc p. 39 audiogain_mng p. 38 v in1thof 4 15 ------ k ?? ?? vbst gain ---------------- - ?? ?? ? = v in1thon 2 3 -- - k ?? ?? vbst gain ---------------- - ?? ?? ? =
ds963f5 17 CS35L32 4.4 low-battery management 4.3.2 class g operat ion with leds on if leds are active, the speaker amplifier supply in one of the following supply modes, as sp ecified by vboost_mng (see section 4.10.3 and section 7.12 for details): ? class g operation defaults to the higher supply setting: th at requested by the leds or that requested by class g. the latter takes into account both thresholds v in1thof and v in1thon , as described in section 4.3.1 . ? class g disabled and the speaker amplifier supply is set as requested by the leds. thresholds are ignored. ? class g disabled where th e boost converter is in bypass mode (vbst = vp). thresholds are ignored. ? class g disabled where the boost converter is in boost mode and vbst = 5 v. thresholds are ignored. 4.3.3 error conditions table 4-2 provides links to error status and mask bits for the class d audio amplifier errors. the CS35L32 monitors the out terminals in real time to determine whether the ou tput voltage signal correlates to the pwm data stream driving the gate drivers internal to the device . if it is not, the CS35L32 in terprets the discrepancy as a short on the outputs, which may have been caused by a short to ground, across the speaker, or to the vbst rail. if this error occurs, the amp_short status bit is set, and, if m_amp_short = 0, int is asserted. as a result, the device enters speaker-safe mode, which is described in section 4.3.4 . the CS35L32 also enters speaker-safe mode if its temp erature exceeds the overtemperature shutdown threshold specified in table 3-3 . the ote status bit is set; if m_ote = 0, int is asserted. the amplifier shuts down automatically due to battery (vp) undervoltage, as described in section 4.5 . the amplifier restarts automatically upon voltage recovery, with default gain. the audio amplifier outputs are clamped to ground if mclk stops, as described in section 4.13.3 . 4.3.4 speaker-safe mode speaker-safe mode is entered according to the am p_short and ote interrupt status bits as follows: ? in the event of an amp_short, the CS35L32 mutes the amplifier output to hi-z to protect the speaker while the boost converter is allowed to operate normally. ? in the event of an ote, the CS35L32 mutes the amplifier output to hi-z to protect the speaker and sets the boost converter in bypass mode ( vbst = vp). normal behavior resumes when the error condition ceases and ote_rls is sequenced as described in section 4.7.1 . ? if speaker-safe mode is entered as a result of an am p_short error, normal behavior resumes when the short condition ceases and the amp_short_rls bit is sequenced as described in section 7.15 . 4.4 low-battery management under heavy current loading, such as a high curr ent led flash event, the battery voltage drops. lowbat_th (see p. 37 ) allows the user to select a voltage threshold, below which flash current is reduced from the led_flcur setting (see p. 43 ) to the led_flinhcur setting (see p. 44 ). upon voltage recovery above lowbat_recov (see p. 37 ), the flash current setting reverts to normal. the user should select a recovery threshold higher than the low-battery threshold. low-battery mode is entered only if a battery voltage falls below the programmed lowbat_th during a flash event. this condition is reported by the setting lowbat (see p. 42 ), which can be masked with m_lowbat (see p. 41 ). int is deasserted after the interrupt registers are cleared by being read, provided the c ondition no longer exists. table 4-2. class d audio amplifier error status and mask bits error cross-reference to description amplifier short/amplifier short mask amplifier short release overtemperature error/overtemperature error mask overtemperature error release amp_short p. 41, m_amp_short p. 40, also see section 4.3.3 amp_short_rls p. 39 ote p. 41, m_ote p. 40, also see section 4.3.3 ote_rls p. 40
18 ds963f5 CS35L32 4.5 undervoltage lockout (uvlo) 4.5 undervoltage lockout (uvlo) if the vp level falls below the lockout threshold specified in table 3-3 , uvlo protection shuts down all analog circuitry of the CS35L32. autorecovery occurs as vp rises above the lockout threshold by a voltage equal to the specified hysteresis. during a uvlo condition, control port, uvlo detection, serial clock, watchdog, and thermal det ection circuitry stay active. note: during an uvlo condition, the i 2 s port is automatically powered down, pr eventing the uvlo condition from being fed back via the adsp sdout pin. 4.6 boost converter the CS35L32's boost converter, shown in fig. 4-3 , delivers power to the supply of the audio speaker amplifier as well as to the leds. its output voltage is determined by vboost_mng (see p. 38 ). section 4.10 further shows how vboost_ mng relates to audio and led operation. the boost converter features a current-limiting circ uit that detects and clamps peak inductor current if such a peak is equal to the user-programmable limit ( bst_ipk , see p. 38 ). boost_curlim interrupt flag is set when the current limit has been detected. mclk int sets the frequency of the converter to 2 mhz. mclk int is derived from mclk by setting mclkdiv2 (see p. 37 ). if mclk int stops switching, the converter is placed in bypass mode until clocking is restored. figure 4-3. boost controller block diagram 4.7 die temperature monitoring onboard die temperature monitoring prevents, shown in fig. 4-4 , the CS35L32 from reaching a temperature that would compromise reliability or functionality. the CS35L32 incorporates a two-thresh old thermal-monitoring system. when die temperature exceeds the lower threshold, an overtemperature warning (otw) even t occurs; if it exceeds the second threshold, an overtemperature error (ote) conditi on occurs. these conditions are described in section 4.7.1 . figure 4-4. die temperature monitoring note: the CS35L32 does not support independent powering do wn of die-temperature monitoring circuitry (other than powering it down via pdn_all , see p. 36 ). boost converter vp vbst vp sw rectifying fet gndp boost controller 2-mhz clock set reset pulse width control r bst_sns iref gen v bandgap internal reference circuitry iref+ c bst(out) c bst(in) boost fet l bst bst_ipk on p. 38 die temperature monitoring temperature sensor va v bandgap overtemperature error reference (t op ) v bandgap overtemperature warning reference (t wrn ) otw on p. 41 m_otw on p. 40 (see section 4.7.1 ) ote on p. 41 m_ote on p. 40 ote_rls on p. 40 (see section 4.7.1 )
ds963f5 19 CS35L32 4.8 signal monitoring 4.7.1 error conditions table 4-3 lists overtemperature error status and mask bits. the overtemperature error and warning error conditions are described in detail in the following: ? overtemperature warning (otw). an otw event occurs when the die temperature exceeds the overtemperature threshold (listed in table 3-3 ). when this occurs, an otw (see p. 41 ) event is registered in the interrupt status ( section 7.19 ); if m_otw = 0, int is asserted. to exit the condition, the temperature must drop below t he threshold and interrupt status 1 register must be read. ? overtemperature error (ote). an ote event occurs when the die temperature exceeds the internally preset error threshold (see table 3-3 ). when this occurs, an ote (see p. 41 ) event is registered in the interrupt status and, if m_ote =0, int is asserted. the CS35L32 shuts down, the class d amplifier enters speaker safe mode, as described in section 4.3.4 , and the led drivers shut down. to exit, the temperature must drop below the overtemperature shutdown threshold and ote_rls must be sequenced as described in section 7.15 . after ote release, the amplifier and led drivers recover to preshutdown settings. the led drivers must be retriggered with fl en and/or flinh inputs for a lighting event to occur. 4.8 signal monitoring signal-monitoring adcs, shown in fig. 4-5 , give upstream system processors a ccess to important si gnals entering and exiting the device. the three monitoring signals are as follows: ? vpmon: monitors the voltage on the vp pin, which is most commonly the battery for the system. ? vmon: monitors the output voltage of the class d amplifier. ? imon: monitors the current that flows into the load being driven by the class d amplifier. an integrated adc digitizes these analog si gnals, at which point, the audio/data serial port (adsp) can send them to the system processor. figure 4-5. signal monitoring block diagram (pdn_xmon = 0) 4.8.1 power-up and power-down bits (pdn_xmon) the three adcs can be powered down independently via t heir respective pdn_xmon bit in the control port, see section 7.6 . to power down an adc and its associated support ci rcuitry, its pdn_xmon bit must be set; clearing pdn_ xmon powers up the corresponding circuitry. note: for proper operation, mclk must be at the correct frequency ( mclk_err =0; see p. 41 ) and the device must be powered ( pdn_all = 0; see p. 36 ). table 4-3. die temperature monitoring configuration error cross-reference to register field description overtemperature error/overtemperature error mask overtemperature warning/overtemperature warning mask overtemperature error release ote p. 41/m_ote p. 40 otw p. 41/m_otw p. 40 ote_rls p. 40 signal monitoring vsense+ multibit ?? adc vsense? isense+ isense? multibit ?? adc to audio/ data serial port vp (3.0?5.25 v) multibit ?? adc range scaling ?30 to +36 db 6-db steps vmon adc front end lp imon adc front end lp imon_scale on p. 38 (pdn_xmon = 0)
20 ds963f5 CS35L32 4.8 signal monitoring 4.8.2 monitoring voltage across the load?vmon as shown in fig. 4-5 , monitoring on vmon is accomplished via the vsense pins. table 3-7 gives operating and performance specifications for this adc path. the following equation determines the vmon voltage (in volts): d out is the 16-bit digital output monitoring word in signed de cimal format (?32,768 to +32,7 67) and va is the voltage on the va pin. relative to vsense+, negative d out values equate to a negative load voltage and positive d out values equate to a positive load voltage. when va is 1.8 v, the full-scale signal is 6.25 v. if vmon is a 12-bit word, its equivalent 16-bit representation for the computational purposes of this section positions the 12 bits in the 12 msbs and the 4 lsbs are cleared in the computation. 4.8.3 monitoring curren t through the load?imon as shown in fig. 4-5 , monitoring of output current is accomplished vi a the isense pins, which are provided to measure a voltage drop across a sense resistor in the output path, as described in section 3 . a precision resistor ( ? 1%) is chosen for high accuracy when calculating the current from the volt age measured across the resistor. likewise, to avoid thermal drift, the resistor is chosen to have a low thermal coefficient of 100 ppm/c. table 3-7 gives operating and performance specifications for this adc path. the following equation determines the imon current (in amps) when using a 0.1- ? sense resistor: d out is the 16-bit digital output monitoring word in signed de cimal format (?32,768 to +32,7 67) and va is the voltage on the va pin. relative to isense+, negative d out values equate to a negative current and positive d out values equate to a positive current. the default imon_scale, as described in section 4.8.3.1 , is used for the example equation. if the imon_scale value is increased by 1 bit, the 2 15 power in the imon equation increases to 2 15+1 . if the imon_scale value is decreased by 1 bit, the 2 15 power in the imon equation decreases to 2 15?1 . if imon is a 12-bit word, its equivalent 16-bit representation for the computational purposes of this section positions the 12 bits in the 12 msbs, and the 4 lsbs are cleared in the computation. 4.8.3.1 imon signal scaling (imon_scale) because the voltage is measured across a resistor of very sm all value and because output current can vary significantly depending on the program material, a gain-scaling block (shown in fig. 4-5 ) is included to improve the reported sample resolution for low-level signals. this control, configured through imon_scale (see p. 38 ), allows the system processor to determine the rang e of bits to be received from the available 26-bit word on the imon adc?s data bus. the default imon_scale configuration (22 down to 7) configures the adc data msb (bit 22) to be the 16-bit imon data packet msb. adc bits 23?25 allow the signal to be divided down. if imon is a 12-bit word, its equivalent 16-bit representation for the computational purposes of this section positions the 12 bits in the 12 msbs. the 4 lsbs are cleared in the computation. 4.8.3.2 imon sense resistor a 0.1- ?? sense resistor is used to generate a di fferential voltage that is captured by the imon circuitry to monitor the load current. if pwm output filtering components, such as ferrite beads, are placed in series with the output load, the sense resistor must be placed betw een the spkout+ pin and the exte rnal series filter componen t, minimizing any performance effects produced by the output filter. if th e sense resistor is placed after the se ries-filtering component, the signal being measured across the sense resistor will hav e been altered from its expected form. vmon d out 2 15 1 ? ------------------- ?? ?? ?? 6.25 va ? 1.8 ------------------------- - ?? ?? ? = imon d out 2 15 1 ? ------------------- ?? ?? ?? 0.82 va ? 0.1 ? ------------------------- - ?? ?? ? =
ds963f5 21 CS35L32 4.9 led driver 4.8.4 monitoring voltag e on the vp pin?vpmon monitoring of the voltage present on the vp pin is integrated internally to the cs 35l32. the operating specifications for this adc path are given in table 3-7 . to determine the voltage present on vp, the following equation must be used: d out is the digital output word (see vpmon , p. 38 ) in signed decimal format (?128 to +127), and va is the voltage on the va pin. if va = 1.8 v, vpmon can report values from 2.8 v (d out = ?77 decimal) to 5.52 v (d out = 0 decimal). 4.8.5 data transmission out of the CS35L32 the adsp, described in section 4.11 , can transmit all signals monitored in the CS35L32 to the system processor. the data is presented on these outputs simultaneously. 4.8.6 error conditions the CS35L32 monitors each monitori ng adc for overflow conditions. table 4-4 lists signal monitoring error conditions and provides links to their associated register field descriptions. if an overflow occurs, the appropriate xmon_ovfl bit is set, a nd, if the respective mask bit is cleared, an interrupt occurs. exiting the error occurs when the signal is no longe r overflowing. no release bit needs to be toggled. ? overflow for vpmon and vmon signals. due to the anal og prescaling applied to the analog input signals, which are sampled to make the vpmon and vmon signals, ov erflow conditions are unlikely on these adcs. this is because the operating specifications for maximum and mi nimum voltage constrain the voltage on these pins to a level far below that required to make the adc overflow. for vpmon, because a spurious overflow error can occur when the block is taken out of power down, it is advised to read the error status registers after pdn_xmon has been cleared to clear the spurious error status bit. ? overflow for the imon signal. as section 4.8.3.1 describes, the imon_scale (see p. 38 ) control allows the greatest possible sample resolution over a wide range of output currents and sense re sistors. if imon_scale is set too low for either the output current being monitored or the sense resistor being used, overflow of this adc can occur. when this error occurs, increasing the imon_scale value can prevent the sampled signal from overflowing. 4.9 led driver the CS35L32 includes a high-current flash led driver (see fig. 4-6 ), featuring two channels, flout1 and flout2, and a boost converter and current regulator designed to power leds with up to 0.75 a per channel. both channels can be combined to drive an led with 1.5 a by tying flout1 and flout2 together. figure 4-6. led dri ver block diagram table 4-4. signal monitoring error status conditions error cross-reference to description xmon overflow. indicates the overrange status in the vmon, imon, or vpmon adc signal paths. vmon_ovfl p. 42 imon_ovfl p. 42 vpmon_ovfl p. 42 vp d out 128 + ?? 255 --------------------------------------- 5 ? 1 1.8 ------- - + ?? ?? va ? = flash led current drivers control, sensing, and fault protection flout1 flout2/ad0 flen flinh i 2 c control port current mode boost controller gndpled led_flinhcur on p. 44 led_flcur on p. 43 led_mvcur on p. 44 timer on p. 44 timeout_mode on p. 44
22 ds963f5 CS35L32 4.9 led driver the CS35L32 is driven to flash when flen is asserted high. the i 2 c interface allows a host to program flash and movie mode currents, as well as a flash timer. the co rresponding registers for these settings are led_flcur (see p. 43 ), led_ mvcur (see p. 44 ), and timer (see p. 44 ). the flash event terminates at the e nd of a period determined by the flash timer and optionally when flen is deasse rted; this option is configured through timeout_mode (see p. 44 ). flash current is reduced if flinh is asserted . currents in both channels are reduced to the led_flinhcur setting (see p. 44 ). if flinh is deasserted, the current reverts to the led_flcur setting, subject to the flash timer state. movie mode operation has no timer and starts and ends according to the led_mvcur setting. fig. 4-7 shows how flash and flash inhibit mode current s are started and terminated. to power the led load, the led driver and current regulato r automatically boost the voltage if battery operation is insufficient to produce the required led currents. the controller bases whether to boost or operate in bypass, based on maintaining a minimum voltage across the current regulator. the boost voltage varies by up to 5 v nominal, as described in section 4.10 and section 7.12 , depending on user selection. figure 4-7. led flash timing diagram 4.9.1 led driver protection the led controller shuts down if the CS35L32?s temperature exceeds the overtemperature shutdown threshold specified in table 3-3 . the ote status bit is set and, and if m_ote = 0, int is asserted. recovery star ts after the user clears ote_ rls (see p. 40 ), after which, the led drivers must be retriggered with a flen signal for a flash event to occur, or with the ledx_mven enable bit (see section 7.24 ) for a movie mode event to occur. an automatic led driver shutdown occurs in the event of a shorted or open led. led open and short conditions are detected only when a flash or movie mode event is initiated. for a flash mode event to occur after clearing the error status bit, the led drivers must be retriggered with a flen signal. fo r a movie mode event to occur after clearing the error status bit, the ledx_mven bit must be set. 4.9.2 led driver interrupt an interrupt is generated when any of the following conditions or faults occur: ledx short or open is present when a flash event is initiated, current limit, boost output overvoltage, or uvlo of vp. the condition is registered in interrupt status register 3, section 7.21 . its mask is in section 7.18 . if the error conditions are no longer present, i nt is reset and deasserted after the interrupt register is read. note: the device does not generate an led open circuit inte rrupt if the boost converter is running in bypass mode (pdn_bst= 01). t flash t flash flash off flash flash flash inhibit flash t flash flash off off off led current flen flinh flash inhibit (timeout_mode = 1) flash inhibit t flash
ds963f5 23 CS35L32 4.10 power budgeting 4.9.3 led lighting status register the led lighting stat us register (see section 7.22 ) reports the state of leds and their controls. status is reported for led1 and led2 flash events, indicating whether each led is driven with current set by the flash setting. likewise, status is reported for led1 and led2 movie mode events, indicating wh ether each led is driven with current set by the movie mode setting. led2 disable status is reported if flout2 is used without an led and is tied to ground, as shown in fig. 2-1 . the logic status of the signal in put at flen and flinh is reported . flash timer events are reported. 4.10 power budgeting power budgeting is configured through iled_mng , audiogain_mng , and vboost_mng (see p. 38 ), which set the boost converter?s output mode and the load management mode, as described in section 4.10.1 ? section 4.10.3 . load management consists of reducing audio or led load, or both , as long as one of the following conditions exists: ? the boost converter output voltage ha s dropped, provided that the boost conv erter is configured for a fixed 5-v mode through vboost_mng and the load current has settled to its target value. ? the boost converter is in current limit. ? an overtemperature warning (135c) has occurred. power budgeting is configurable to be active automatica lly without user interventi on, semiautomatically, or nonautomatically, where the user cont rols audio and led load management. fig. 4-8 shows power budgeting. figure 4-8. power budgeting block diagram 4.10.1 audio-only operation if only audio is operating, there are no power-budgeting concerns. as a default, the boost converter?s output voltage is fixed in bypass mode (vbst = vp). the us er can set vboost_mng (see p. 38 ) to any of the nondefault modes for a different boost behavior. refer to section 4.3.1 . 4.10.2 led-only operation if only leds are operating, the user can se lect one of the following courses of action: ? by clearing iled_mng (see p. 38 ), led current is managed automatically. if the CS35L32 enters load management mode due to a condition listed in section 4.10 , the current is iteratively reduced until the condition no longer exists. ? by setting iled_mng, the user main tains full control over led current. as a default, the boost converter?s out put voltage is fixed in bypass mode (vbst = vp). the user can se t vboost_mng to any of the nondefault modes for a different boost behavior. in particular, if vboost_mng = 00 or 01 and load power consists of leds only, the CS35L32 adapts for low power di ssipation by automatically redu cing the led driver voltage (vds) at pins flout1 and flout2 and by reducing the boost converter?s output vo ltage. such operation increases boost converter efficiency, lowers temperature rise in the cs35l 32, and increases battery run time. if vboost_mng is set to 10 or 11, the CS35L32 does not adapt for low-power dissipation because the boost voltage is fixed. flash led current drivers in? ? + in+ class d amplifier overtemperature warning power budgeting controller vds monitor boost drop current limit boost converter otw on p. 41
24 ds963f5 CS35L32 4.11 audio/data serial port (adsp) 4.10.3 audio and led operation when audio and leds are operating simultaneously, the us er can select one of the following courses of action: ? by clearing audiogain_mng, if the CS35L32 enters load management mode due to the conditions listed in section 4.10 , audio gain is reduced once by 3 db (no reduction fo r 9-db gain). if the condition persists, the CS35L32 examines iled_mng and responds according to section 4.10.2 . audio automatically recovers to the original volume after an led event. ? by setting audiogain_mng, the user maintains full control over audio gain. as a default, the boost converter?s out put voltage is fixed in bypass mode (vbst = vp). the user can se t vboost_mng to any of the nondefault modes for a diff erent boost behavior. in particular, if vboost_mng = 01 in the presence of led and audio load power, the CS35L32 adapts for low-power dissipat ion by automatically reducing the led driver voltage at pins flout1 and flout2 and by reducing the boost converter?s output voltage. if vboost_mng = 00 in the presence of led and audio-load power, the boost converter?s output voltage is determined by the higher of the two supply requirements for led or audio class g. in such a case, the CS35L32 cannot adapt for low power dissipation if audio class g requires a 5-v supply, because of the higher audio signal. refer to section 4.3.2 . 4.11 audio/data serial port (adsp) the adsp transmits audio and data to and from the systems pr ocessor in traditional i2s mode. controls are provided to advise the device of the rate of the clocks being applied to its inputs when in slave mode. likewise, the same controls are used to indicate the clock rates to be generated when operating as a clock master. the serial port i/o interface consists of three signals, described in detail in table 1-1 : ? sclk: serial data shift clock ? lrck: provides the left/right clock, whic h identifies the start of each serialized data word and toggles at sample rate ? sdout: serial data output figure 4-9. audio/data serial port (adsp) table 4-5 provides links to register fields us ed to configure components shown in fig. 4-9 . . 4.11.1 power up, power down, and tristate the serial port has separate power-down and tristate controls for its output data path ( sdout_3st , see p. 37 ). adsp master/slave operation is governed only by the m/s setting (see p. 39 ), irrespective of the sdout_3st setting. table 4-6 describes adsp operational mode and pi n-output driver-state configuration. table 4-5. adsp configuration register field cross-re ference to description pdn_amp sdout_3st mclkdis, mclkdiv2, ratio m/s m_adspclk_err adspclk_err section 7.5 section 7.6 section 7.7 section 7.13 section 7.16 section 7.19 level shifters audio data serial port from signal monitoring blocks r onchip channel select lrck sclk onchip serial port rate control l lrck sclk sdout
ds963f5 25 CS35L32 4.11 audio/data serial port (adsp) 4.11.1.1 tristating the ads p sdout path (sdout_3st) if the sdout functionality of the adsp is not required, power losses caused by the charging and discharging of parasitic capacitances on this pin can be eliminated by setting sdout_ 3st, so that the sdout line is tristated. when reactivating sdout, the associated circuits come alive and a fu ll lrck cycle elapses before sdout data is valid. 4.11.2 master and slave timing the serial port operates as either the master of timing or the slave to another device?s timi ng. when the serial port is master, sclk and lrck are outputs; when it is a slave, they are inputs. master/slave mode is configured by the m/s bit. in i2s master mode, the sclk and lrck clock outputs are derived from mclk int . sclk is generated to have approximately 64 cycles per lrck cycle. in slave mode, because there is no sample-rate conversion from the serial port to the device core, the serial port audio sample rate (f lrck ) must equal the core sample rate (fs). to ensure that the CS35L32 maintains synchronization with the serial port sample rate, the ratio divider (see p. 37 ) is programmed to indicate the sample rate to mclk int relationship. table 4-7 shows the corresponding ratio (f mclk(int) f lrck ) for each mclk int at the supported lrck rate. in master mode, in a dual-CS35L32 configuration (see section 4.12.3 ) with mclk int = 6 mhz, a ratio of 125 is not supported. adspclk_err (see p. 41 ) indicates when the adsp attempts to resynchronize due to the absence of an lrck edge at the expected time due to excessive jitte r, misprogramming, or clock absence. note that, given that the clock-checking circuit checks for lrck edges appearing in the expected locati on relative to internal timing, if the lrck frequency is an integer multiple of the expected rate (e.g., the lrck rate is 96 khz [2 x 48 khz] vs. the expected 48 khz), adspclk_err does not detect this error condition. al so note that, since the clock-checking circ uit monitors edges, if lrck is removed and no further clock edges are produced, adspclk_e rr triggers only once while the lrck is removed. table 4-7 lists supported serial-port audio sample rates, their relationship to the mclk int rate, and the programming required to generate a given lrck rate in master mode and ensure the serial port maintains synchronization in slave mode. if all amplifier functionality is not bei ng used, but CS35L32 clock mastering is desired, set up the clocks using the clocking control register controls, then set sdout_ 3st. in this scenario, since the amplifie r is inaccessible, it should be powered down to save power (pdn_amp = 1). 4.11.3 adsp in i 2 s mode the adsp operates in traditional i2s format, with a minor modifi cation. on the transmit side, the data structure is modified to transmit nonconventional data (e.g., the monitored signal s) in a compatible format. receive mode is not supported. 4.11.3.1 data bit depths the data word length of the i2s interface fo rmat is ambiguous. fortunately, the i2s fo rmat is also left ju stified, with a msb- to-lsb bit ordering, which negates the need for a word-length control register. the following text describes how different bit depths are handled with the i2s format. table 4-6. adsp operational mode and pin configurations m/s sdout_3st adsp operational mode sdout pin driver lrck pin driver sclk pin driver 00i 2 s slave mode output input input 01i 2 s slave mode hi-z input input 10i 2 s master mode output output output 11i 2 s master mode hi-z output output table 4-7. adsp rates mclk int rate (mhz) lrck rate (khz) f mclk(int) /f lrck (rate ratio) ratio 6.0000 48.000 125 1 6.1440 48.000 128 0
26 ds963f5 CS35L32 4.12 signaling format the CS35L32 transmits data that is from 24 to 32 bits deep pe r channel sample. if fewer than 24 serial clocks are present per channel frame (half lr clock period), it outputs as many bits as there are clocks. if there are more than 24 serial clocks per channel frame, it outputs the bits shown in the extended section for the additional clock cycles after the 24th bit. any bit beyond the 24th, if marked as reserved, is zero. the rece iving device is expected to load the data in msb-to-lsb order until its word depth is reached, at which point it should discard any remaining lsbs from the interface. 4.12 signaling format the CS35L32 supports the i2s format on its serial port: ? up to 32 bits/channel of composit e data can be sent, as shown in table 4-9 ? table 4-13 . additional bits are packed in the extended section, beyond the 24th bit, and are accessed if a 32-clock frame is used. ? lrck identifies the transmission start of each channel. ? data is clocked out of the sdout ou tput using the falling edge of sclk. ? bit order is msb to lsb. signaling for i2s format is shown in fig. 4-10 . figure 4-10. i2s format 4.12.1 transmitting data the CS35L32 includes real-time monitoring of several signals in ternal and external to the dev ice via integrated adcs, as well as a number of status bits. the monitoring data exists as three signa ls?vpmon, vmon, and imon?which are described in section 4.8 and table 4-8 , which also describes status bits. table 4-8. sdout monitor data description function data descriptor description speaker amplifier section 4.3 . amp_short (amplifier short) indicates that either of the outputs (out+ and/or out?) of the amplifier is driving a short circuit 0 (default) not shorted 1 shorted. when this condition exists, the device enters speaker-safe mode. see section 7.19 and section 4.3.4 . undervoltage lockout (uvlo) section 4.5 . uvlo (uvlo event) 0 (default) no undervoltage lockout 1 uvlo detected at vp. ic shut down. see section 7.21 . boost converter section 4.6 . boost_curlim (boost converter in current limit) 0 (default) boost converter is not in current limit 1 boost converter is in current limit see section 7.21 . boost_overror (boost converter overvoltage error) 0 (default) no overvoltage detected 1 overvoltage detected see section 7.21 . die temperature monitoring , section 4.7 . otw (overtemperature warning) indicates that device junction temperature exceeded the set limit in table 3-3 0 (default) junction temperature is below the set overtemperature warning threshold 1 junction temperature is above set overtemperature warning threshold ote (overtemperature error) indicates whether the device junction temperature exceeded the damage limit 0 (default) junction temperature is below damage limit 1 junction temperature is above damage limit. when this condition exists, the device enters speaker-safe mode. see section 7.19 and section 4.3.4 . lrck sclk sdout msb msb-1 lsb +1 lsb 1/fs ext msb msb-1 lsb +1 lsb msb sclk may stop or continue t extraa = none to some time sclk may stop or continue t extrab = none to some time left (a) channel right (b) channel
ds963f5 27 CS35L32 4.12 signaling format 4.12.2 transmitting data from a single-CS35L32 configuration for a single CS35L32, the user clears share (see p. 39 ). when transmitting data via the adsp, the monitor data is packed as shown in table 4-9 : left channel vmon[15:0], vpmon[7:0] and right channel imon[15:0], status. signal monitoring , section 4.8 . vmon_ovfl (vmon overflow) xmon overflow. indicates the overrange status in the vmon, imon, or vpmon adc signal path 0 (default) no clipping has occurred anywhere in the adc signal path. 1 clipping has occurred in the adc signal path. the programming of imon_scale may cause imon_ovfl to be set. see section 7.20 . imon_ovfl (imon overflow) vpmon_ovfl (vpmon overflow) vmon (voltage monitor) 16- or 12-bit representation of the voltage across the load, sensed on vsense imon (current monitor) 16- or 12-bit representation of the voltage sensed across an external 0.1- ?? resistor in series with the spkout+ terminal, sensed on isense vpmon (battery voltage) 8-bit representation of the voltage present on vp pin, i.e., the system?s battery voltage, sensed internally led driver section 4.9 . led12_flev (led12 flash event) led1 or led2 flash event (logical or of led1_flev and led2_flev , see p. 43 ) 0 (default) no driver flash current delivered to either led1 or led 2 1 flash current delivered to led1, led2, or both led12_mvev (led12 movie mode event) led1 or led2 movie event (logical or of led1_mven and led2_mvev , see p. 43 ) 0 (default) no driver movie current delivered to either led1 or led 2 1 movie current delivered to led1, led2, or both led_timeron (flash timer) flag indicating whether the flash timer is on. see section 7.22 . 0 (default) led flash timer off 1 led flash timer on power down pdn_done (power-down done) indicates whether the CS35L32 is completely powered down and mclk can be stopped. see section 7.20 . 0 not completely powered down. pdn_done = 0 if any blocks still require mclk int . after powering down using pdn_all or the individual power-down bits, the CS35L32 transitions to a powered-down state, after which, pdn_done is set and mclk int can be removed. 1 (default) powered down table 4-9. sdout monitor data positioning (single CS35L32 ) bit bit number left-channel data contents right-channel data contents msb 1 vmon[15] imon[15] msb ? 1 2 vmon[14] imon[14] ??? ? msb ? 15 16 vmon[0] imon[0] msb ? 16 17 vpmon[7] amp_short msb ? 17 18 vpmon[6] otw msb ? 18 19 vpmon[5] ote msb ? 19 20 vpmon[4] vmonimon_ovfl msb ? 20 21 vpmon[3] vpmon_ovfl msb ? 21 22 vpmon[2] pdn_done msb ? 22 23 vpmon[1] boost_curlim msb ? 23 24 vpmon[0] led_timeron msb ? 24 25 reserved vmon_ovfl msb ? 25 26 reserved imon_ovfl msb ? 26 27 reserved uvlo msb ? 27 28 reserved boost_overror msb ? 28 29 reserved led12_flev msb ? 29 30 reserved led12_mvev msb ? 30 31 reserved reserved msb ? 31 32 reserved reserved table 4-8. sdout monitor data description (cont.) function data descriptor description
28 ds963f5 CS35L32 4.12 signaling format 4.12.3 transmitting data from a dual-CS35L32 configuration to indicate a dual-CS35L32 configuration where the sdout line is shared, the user must set share (see p. 39 ). when two CS35L32 devices are available on the same board, each device is identified by its i 2 c address. the ad0 pin is shared by flout2. upon power-up or upon deasserting reset , each CS35L32 reads the ad0 pin logic level and configures its chip address. transmission starts when sdout_3st (see p. 37 ) is cleared. the device 0 address (ad0 level low) transmits its data on the left channel time slot while device 1 is automatically tr istated; the device 1 address (ad0 level high) transmits on the right-channel time slot while device 0 is automatically tristated. the datcnf setting (see p. 39 ) determines data transmission for both CS35L32s, as shown below: ? table 4-10 (datcnf = 00): left and right channe l vmon[11:0], imon[11:0], vpmon[7:0] ? table 4-11 (datcnf = 01): left and right channel vmon[11:0], imon[11:0], status ? table 4-12 (datcnf = 10): left and right channel vmon[15:0], imon[15:0] ? table 4-13 (datcnf): left and right channel vpmon[7:0], status table 4-10. sdout monitor data positioning (two CS35L32s, datcnf = 00) bit bit number left-channel data contents right-channel data contents msb 1 vmon[11] device 0 vmon[11] device 1 msb ? 1 2 vmon[10] device 0 vmon[10] device 1 ??? ? msb ? 11 12 vmon[0] device 0 vmon[0] device 1 msb ? 12 13 imon[11] device 0 imon[11] device 1 msb ? 13 14 imon[10] device 0 imon[10] device 1 ??? ? msb ? 23 24 imon[0] device 0 imon[0] device 1 msb ? 24 25 vpmon[7] device 0 vpmon[7] device 1 msb ? 25 26 vpmon[6] device 0 vpmon[6] device 1 ??? ? msb ? 31 32 vpmon[0] device 0 vpmon[0] device 1 table 4-11. sdout monitor data positioning (two CS35L32s, datcnf = 01) bit bit number left-channel data contents right-channel data contents msb 1 vmon[11] device 0 vmon[11] device 1 msb ? 1 2 vmon[10] device 0 vmon[10] device 1 ??? ? msb ? 11 12 vmon[0] device 0 vmon[0] device 1 msb ? 12 13 imon[11] device 0 imon[11] device 1 msb ? 13 14 imon[10] device 0 imon[10] device 1 ??? ? msb ? 23 24 imon[0] device 0 imon[0] device 1 msb ? 24 25 amp_short device 0 amp_short device 1 msb ? 25 26 otw device 0 otw device 1 msb ? 26 27 ote device 0 ote device 1 msb ? 27 28 vmonimon_ovfl device 0 vmonimon_ovfl device 1 msb ? 28 29 vpmon_ovfl device 0 vpmon_ovfl device 1 msb ? 29 30 pdn_done device 0 pdn_done device 1 msb ? 30 31 boost_curlim device 0 boost_curlim device 1 msb ? 31 32 led_timeron device 0 led_timeron device 1 table 4-12. sdout monitor data positioning (two CS35L32s, datcnf = 10) bit bit number left chan nel data contents right channel data contents msb 1 vmon[15] device 0 vmon[15] device 1 msb ? 1 2 vmon[14] device 0 vmon[14] device 1 ??? ? msb ? 15 16 vmon[0] device 0 vmon[0] device 1 msb ? 16 17 imon[15] device 0 imon[15] device 1 msb ? 17 18 imon[14] device 0 imon[14] device 1 ??? ? msb ? 31 32 imon[0] device 0 imon[0] device 1
ds963f5 29 CS35L32 4.13 device clocking 4.13 device clocking the device can operate as a clock master, creating both sclk and lrck for itself and for othe r devices in the system. it can also be operated as a clock slave, receiving the sclk and lr ck signals as input. in either case, internal controls are used to advise (in slave mode) or set (i n master mode) the clocking relationships among the externally applied mclk, the internally derived mclk (mclk int ), sclk, and lrck. 4.13.1 internal master clock generation an internal clock (mclk int ) is derived from the clocking signal that dr ives the mclk pin. the user must configure mclkdiv2 (see p. 37 ) so the proper internal mclk signal can be deri ved. when the external clock is 6 or 6.144 mhz, mclk int can simply be a buffered version of the clock that driv es the mclk pin. this is done by clearing mclkdiv2. however, if the external clock is 12 or 12.288 mhz, it must be halv ed to achieve an mclk int rate of approximately 6 mhz. this is done by setting mclkdiv2. table 4-14 outlines the supported internal mclk int nominal frequency and how it is derived from the supported frequencies of the external mclk source (mclk input pin). to save power, mclk can be disabled by setting mclkdis (see p. 37 ). 4.13.2 adsp device clocking the CS35L32 can operate as a clock master, creating both sclk and lrck for itself and for other system devices. it can also operate as a clock slave, receiving sclk and lrck si gnals as inputs. in master mode, CS35L32 determines clocking relationships among sclk, lrck, and the externally applied mclk. table 4-13. sdout monitor data posi tioning (two CS35L32s, datcnf = 11) bit bit number left channel data contents right channel data contents msb 1 vpmon[7] device 0 vpmon[7] device 1 msb ? 1 2 vpmon[6] device 0 vpmon[6] device 1 ??? ? msb ? 7 8 vpmon[0] device 0 vpmon[0] device 1 msb ? 8 9 amp_short device 0 amp_short device 1 msb ? 9 10 otw device 0 otw device 1 msb ? 10 11 ote device 0 ote device 1 msb ? 11 12 vmonimon_ovfl device 0 vmonimon_ovfl device 1 msb ? 12 13 vpmon_ovfl device 0 vpmon_ovfl device 1 msb ? 13 14 pdn_done device 0 pdn_done device 1 msb ? 14 15 boost_curlim device 0 boost_curlim device 1 msb ? 15 16 led_timeron device 0 led_timeron device 1 msb ? 16 17 vmon_ovfl device 0 vmon_ovfl device 1 msb ? 17 18 imon_ovfl device 0 imon_ovfl device 1 msb ? 18 19 uvlo device 0 uvlo device 1 msb ? 19 20 boost_overror device 0 boost_overror device 1 msb ? 20 21 led12_flev device 0 led12_flev device 1 msb ? 21 22 led12_mvev device 0 led12_mvev device 1 msb ? 22 to msb ? 31 23?32 reserved reserved table 4-14. internal master clock generation mclk rate (mhz) required divide ratio mclk int rate (mhz) settings for mclkdiv2 6.0000 1 6.0000 0 12.0000 2 1 6.1440 1 6.1440 0 12.2880 2 1
30 ds963f5 CS35L32 4.14 control port operation 4.13.3 error conditions mclk, sclk, and lrck are monitored for clocking and configuration errors. if an mclk or adsp error occurs, the respective mclk_err or adspclk_err bit is set, an d, if the respective mask bit is cleared, int is asserted. ? mclk error (mclk_err). if mclk were to stop abruptly wh ile the boost converter or amplifier?s output stages are switching, it could damage or destroy the device. becaus e of this, the CS35L32 integrates a watchdog circuit to monitor mclk frequency. to prevent damage, if mclk is removed or drops below ~1.25 mhz, the boost converter is placed in bypass mode and audio and led operations are shut down. the class d amplifier immediately stops switching and both outputs are internally clamped to ground . after such a disturbance, once a proper mclk can be applied, the device should be reset to ensure recovery to a known state. whenever the mclk watchdog det ermines that mclk is too sl ow, the event is recorded in mclk_err (see p. 41 ). if mclk_err is set, the de vice must be reset (reset = high ?? low), released from reset (reset = low ?? high) once a valid mclk is reapplied, and then restarted adhering to the specifications in table 3-11 . once restarted, default audio functionality resumes with the boos t converter in bypass mode. registers must be reloaded, since the reset operation will ha ve cleared them. ? adspclk error (adspclk_err). if th e adsp ratio is not configured properly for the mclk and audio clocks supplied to the CS35L32, an adsp error is triggered ( adspclk_err = 1, see p. 41 ). section 4.11.2 describes adspclk_err and how to configure the adsp. the CS35L32 monitors the mclk int -to-lrck ratio to determine whethe r it is valid according to the ratio setting (see p. 37 ). if it is invalid, an adspclk_err er ror occurs and, if m_adspclk_err = 0, int is asserted. while the adsp is attempting to correlate the incoming cloc ks to the settings of the ratio controls, the state machine may flag the error condition several times, causing multiple assertions of the int pin. to avoid this, the mask bit for this error can be set after the initial noti ce, followed by the actions from a service routine to clear the error, and then clearing the mask bit once the service routine has run. this error is cleared automatically when th e ratio matches the control port settings. 4.14 control port operation the control port is used to access the registers allowing the amplifier and led drivers to be configured for the desired operational modes and formats. control port operation can be asynchronous with respect to the audio sample rates. however, to avoid potential interference problems, the control-port pins should re main static if no operation is required. the control port operates using an i2c interface with the ampl ifier acting as a slave device. device communication should not begin until the reset and power-up timing requirements specified in table 3-11 and table 3-13 are met. note: the va and vp supplies are needed for proper control- port operation. additionally , although registers can be written to and read from while mclk is powered down, a valid mclk is required to advance the state machines affected by register settings. 4.14.1 i2c interf ace and protocol the serial control-port data pin, sda, is a bidirectional data line. data is clocke d into and out of the CS35L32 by the i2c clock, scl. the signal timings for read and write cycles are shown in fig. 4-11 ? fig. 4-13 . a start condition is defined as a falling transition of sda while the clock is high. a stop condition is defined as a rising transition of sda while the clock is high. all other sda transition s occur while the clock is low. the first byte sent to the CS35L32 after a start condit ion consists of a 7-bit chip address field and a r/w bit (high for a read, low for a write) in the lsb. to communicate with the CS35L32, the i 2 c slave address, shown in fig. 4-11 , should match 100 0000 if the ad0 pin is at level 0, an d should match 100 0001 if it is at level 1.
ds963f5 31 CS35L32 4.14 control port operation figure 4-11. control-port timing?i 2 c writes with autoincrement the logic state of flout2/ad0 c onfigures the i2c device address upon a devic e power up, after reset has been deasserted. the bit labeled ad0 in the address byte in fig. 4-11 reflects the logic state of pin flout2/ad0. if the i2c operation is a write, the next byte is the memory address pointer (map) ; the 7 lsbs of the map byte select the address of the register to be read or written to next. th e msb of the map byte, incr, se lects whether autoincrementing is to be used (incr = 1), allowing successive reads or writes of consecutive registers. each byte is separated by an acknowledge bit, ack, which th e CS35L32 outputs after each input byte is read and is input to the CS35L32 from the microcontroller after each transmitted byte. also for writes, bytes fo llowing the map byte are written to the CS35L32 regi ster addresses pointed to by the last received map address plus however many autoincrements have occurred. fig. 4-11 shows a write pattern with autoincrementing. if the operation is a read, the contents of the register pointed to by the last received map address plus however many autoincrements have occurred, are output in the next byte. fig. 4-12 shows a read pattern following the write pattern in fig. 4-11 . notice how read addresses are based on the map byte from fig. 4-11 . figure 4-12. control-po rt timing?i2c reads with autoincrement if a read address different from that based on the last re ceived map address is desired, an aborted write operation can be used as a preamble that sets the desired read address. this preamble technique is shown in fig. 4-11 , in which a write operation is aborted (after the ack for t he map byte) by sending a stop condition. figure 4-13. control- port timing?i2c reads with preamble and autoincrement the following pseudocode illustrates an aborted write operation followed by a single read operation when the ad0 bit in the slave address is 0. for multip le read operations, autoincrement would be set to on (as shown in fig. 4-13 ). send start condition. send 10000000 (chip address and write operation). receive acknowledge bit. send map byte, autoincrement off. 4 5 6 7 24 25 scl chip address (write) map byte data data start stop ack ack sda 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data sda source master master master pullup slave slave slave slave master pullup ack ack 1 x x x x x x x map addr incr = 1 slave address 1 0 0 0 0 0 x 0 r/w = 0 data to addr x+1 data to addr x+n master master slave data to addr x 7 6 1 0 7 6 1 0 ad0 scl data stop ack ack sda 7 0 7 0 chip address (read) start 7 0 no 25 8 9 18 4 5 6 7 0 1 2 3 16 17 34 35 36 ack slave address 1 0 0 0 0 0 x 1 r/w = 1 data data data from addr x+n+1 data from addr x+n+2 data from addr x+n+3 sda source master pullup slave slave slave master master master pullup 27 ad0 scl chip address (write) map byte data start ack stop ack ack ack sda 7 0 7 0 chip address (read) start 1 x x x x x x x 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack stop map addr = z incr = 1 slave address 1 0 0 0 0 0 x 0 r/w = 0 slave address 1 0 0 0 0 0 x 1 r/w = 1 data data data from addr z data from addr z+1 data from addr z+n sda source master master master pullup slave slave slave slave slave master master master pullup ad0 ad0
32 ds963f5 CS35L32 5 applications receive acknowledge bit. send stop condition, aborting write. send start condition. send 10000001 (chip address and read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. note: for i 2 c reads, the interrupt status regist ers and the register at the address that precedes an interrupt status register must be read individually and not as a part of an autoincremented control-port read. an autoincremented read of any of these registers may clear the contents of an interrupt status register and return invalid interrupt status data. as a result, if an unmasked interrupt condition had caused the int pin to be asserted, the autoincremented read that prematurely clears the corresponding interrupt status bit causes int to be deasserted. therefore, to avoid affecting interrupt status register co ntents, interrupt status registers and the register at the preceding address (specifically, registers at addre sses 0x14?0x17) must only be read individually. 5 applications 5.1 required ? reserved ? register ? configuration the following initialization seq uence must be written after the release of reset but before power down bit is cleared: ? write register 0x00 with the value 0x99. ? write register 0x43 with the value 0x01. ? write register 0x00 with the value 0x00. to address the issue where a small dip can be seen in the audio output signal as the amplifier enters clipping, the following i 2 c sequence must be wr itten at initialization: ? write register 0x00 with the value 0x99. ? write register 0x3b with the value 0x62. ? write register 0x3c with the value 0x80. ? write register 0x00 with the value 0x00. to address the issue where spurious tones exists on both the imon/vmon adcs during idle channel conditions, the following i 2 c sequence must be written at initializatio n to reduce the amplitude of these tones: ? write register 0x00 with the value 0x99. ? write register 0x24 with the value 0x40. ? write register 0x00 with the value 0x00. by default, the boost converter output is in correct if vp exceeds 3.7 v. when a boost event is requested in this condition, the boost converter output is 5.8 v instead of the nominal 5 v. the following i 2 c sequence must be written at init ialization to correct this behavior: ? write register 0x00 with the value 0x99. ? write register 0x49 with the value 0x56. ? write register 0x00 with the value 0x00. 5.2 avoiding current transients when issuing a flash event when the boost converter is configured in either of the two automatic managed modes (vboost_mng = 00 or vboost_ mng = 01) and a flash led event is indicated, a current transi ent can be seen at the output of the boost converter (vbst) through floutx whenever a voltage b oost is requested. the duration of th is transient is approximately 200 ? s. a current transient is also observed in the current that sources vp. the led current settles to the programmed value in the led_ flcur field after the current transient.
ds963f5 33 CS35L32 5.3 external component and pcb design considerations?emi output to avoid the current transient on the vp node, the boost conv erter management must be conf igured for a fixed 5-v boost operation (vboost_mng = 11) before issuing a flash ev ent. vboost_mng may be reconfigured to the desired management mode after a flash event. the following sequence should be followed when issuing a flash event: ? configure vboost_mng to fixed 5-v mode (vboost_mng = 11). ? trigger a flash event by asserting flen. ? wait for the expiration of the flash timer period. 5.3 external component and pcb design considerations?emi output filtering in a portable application, it is import ant not only to pass far-field radiated emissions compliance testing such as fcc part 15 or en55022, but to minimize near-field emissions. in general, far-field compliance testing ensures that an electronic device does not interfere with other electronic devices. also, near-field emissions are more of a concern when ensuring that an electronic device does not interfere with it self. as the name indicates, nea r-field emissions typically do not propagate far enough to in terfere with another device. depending on system characteristics (e.g ., pcb layout, stack-up, supply decouplin g, the connection length to the load, presence of external shielding, sensit ivity of other devices on the system, and proximity to any sensitive devices or antennas), an emi reduction may be necessary over the pe rformance of what is obtained with the typical connection diagram (see fig. 2-1 ). because most class d amplifier emissions are pr oduced or transmitted via the output stage, changes are typically lim ited to adding passive filter ing to spkout+ and spkout?. fo r sensitive sys tems, it is recommended to add a ferrite-bead capacitor (fb-c) output filter to help ensure sufficient attenuation of the high-frequency energy. fig. 5-1 shows recommended vmon and imon connection s where an fb-c output filter is used. figure 5-1. vmon and imon connections with fb-c emi filtering 5.4 pcb routing consider ations for thermal relief due to the thermal dissipation properties inherent to a wafer-level chip sca le package (wlcsp)?and because the CS35L32 contains a boost converter, class d amplifier, and led driver, which can dissipate a fair amount of thermal energy?the pcb design should account for how to remove heat from the device. the simplest approach is to take advantage of as many gnd ba ll locations as possible and connect them in a manner that allows for good thermal conduction. fo r example, a 10-mil diameter, 6-mil dr ill through-hole micr ovia under each nonblocking gnd ball location wo uld allow thermal energy to transmit through the pcb and reach the back-side surface, where it dissipates most effectively. for reference purpose, gnd balls are b5, c2, c3, c5, as shown in gray in fig. 5-2 . generic simulated speaker load 33 ? h r sense 0.1 ? 8 ? spkout+ isense+ isense?/vsense+ spkout?/vsense? fb out fb out spk+ spk? c out c out
34 ds963f5 CS35L32 5.5 inductor selection figure 5-2. ground ball locations (shown in gray) also, as space permits, traces should be wider than 12 mils as soon as they clear the balls of the device. the traces should remain wide for at least 300 mils after they leave the device. 5.5 inductor selection table 5-1 , ?recommended inductors,? lists the inductors recommended for use with the CS35L32 . table 5-1. recommended inductors manufacturer part number inductance dc resistance saturation current 1 1.indicates the inductor?s saturation cu rrent corresponding to a 30% drop in in ductance from the nominal value. height cyntec pst031b-1r0ms 1.0 ? h 8.5 m ? 3.9 a 1.2 mm cooper mpi4040r1-1r0-r 1.0 ? h40 m ? 7.7 a 1.2 mm ball a1 location indicator
ds963f5 35 CS35L32 6 register quick reference 6 register quick reference default values are shown below the bit names. i2c address: ad0 = 0: 1000000[r/w ] ? 10000000 = 0x80 (write); 10000001 = 0x81 (read); ad0 = 1: 1000001[r/w ] ? 10000010 = 0x82 (write); 10000011 = 0x83 (read) adr. function 7 6 5 4 3 2 1 0 0x01 device id a and b (read only) devida[3:0] devidb[3:0] p. 36 00110101 0x02 device id c and d (read only) devidc[3:0] devidd[3:0] p. 36 10100011 0x03 device id e (read only) devide[3:0] ? p. 36 00100000 0x04 reserved ? 00000000 0x05 revision id (read only) arevid[3:0] numrevid[3:0] p. 36 xxxxxxxx 0x06 power control 1 pdn_amp ? pdn_bst[1:0] ? pdn_all p. 36 00000100 0x07 power control 2 pdn_vmon pdn_imon pdn_vpmon ? sdout_3st ? p. 37 11101000 0x08 clocking control mclkdis mclkdiv2 ? ratio p. 37 01000000 0x09 low battery thresholds ? lowbat_th[1:0] lowbat_recov[2:0] ? p. 37 00100110 0x0a battery voltage monitor (read only) vpmon[7:0] p. 38 00000000 0x0b boost converter peak current protection control bst_ipk[7:0] p. 38 01000000 0x0c scaling ? imon_scale[3:0] p. 38 00000111 0x0d led and audio power- budget management ?iled_mng audiogain_mng ? vboost_mng[1:0] p. 38 00000010 0x0e reserved ? xxxxxxxx 0x0f adsp control adsp_drive m/s datcnf[1:0] share ? p. 39 00100000 0x10 class d amplifier control ? amp_gain[2:0] gain_chg_zc ? p. 39 00010100 0x11 protection release control ? amp_short_rls ? ote_rls p. 39 00000000 0x12 interrupt mask 1 ? m_adspclk_err m_mclk_err m_amp_short m_otw m_ote p. 40 11111111 0x13 interrupt mask 2 m_vmon_ovfl m_imon_ovfl m_vpmon_ovfl ? m_pdn_done p. 40 11111111 0x14 interrupt mask 3 m_uvlo m_led2_open m_led2_ short m_led1_open m_led1_ short m_lowbat m_boost_ curlim m_boost_ overror p. 41 11111111 0x15 interrupt status 1 (audio) (read only) ? adspclk_err mclk_err amp_short otw ote p. 41 xxxxxxxx 0x16 interrupt status 2 (monitors) (read only) vmon_ovfl imon_ovfl vpmon_ovfl ? pdn_done p. 42 xxxxxxxx 0x17 interrupt status 3 (leds and boost converter) (read only) uvlo led2_open led2_short led1_open led1_short lowbat boost_ curlim boost_ overror p. 42 xxxxxxxx 0x18 led lighting status (read only) led1_flev led2_flev led1_mvev led2_mvev led_flen led_flinh led2_dis led_timeron p. 43 xxxxxxxx 0x19 led flash mode current ? led_flcur[3:0] p. 43 00000000 0x1a led movie mode current ? led_mvcur[2:0] ? led1_mven led2_mven p. 44 00000000 0x1b led flash timer ? timer[4:0] timeout_mode p. 44 00100100 0x1c led flash inhibit current ? led_flinhcur[3:0] p. 44 00000000 0x1d ?0x7f reserved ? xxxxxxxx
36 ds963f5 CS35L32 7 register descriptions 7 register descriptions all registers are read/write except for the chip id and revision register and the status regist ers, which are read only. the user must not change reserved re gisters from their default state. 7.1 device id a and b address 0x01 r/o 76543210 devida[3:0] devidb[3:0] default00110101 7.2 device id c and d address 0x02 r/o 76543210 devidc[3:0] devidd[3:0] default10100011 7.3 device id e address 0x03 r/o 76543210 devide[3:0] ? default00100000 bits name description 7:4 devida, devidc, devide device id code for the CS35L32. devida 0x3 devidb 0x5 devidc 0xa represents the ?l? in CS35L32 . devidd 0x3 devide 0x2 3:0 devidb, devidd 7.4 revision id address 0x05 r/o 76543210 arevid[3:0] numrevid[3:0] defaultxxxxxxxx bits name description 7:4 arevid alpha revision. arevid and numrevid form the complete device revision id (e.g., a0, b2). 0xa a ? 0xf f 3:0 numrevid numerical revision. arevid and numrevid form the complete device revision id (e.g., a0, b2). 0x0 0 ? 0xf f 7.5 power control 1 address 0x06 r/w 76543210 pdn_amp ? pdn_bs t[1:0] ? pdn_all default00000100 bits name description 7 pdn_ amp power down class d amplifier. configures the power state of the class d amplifier. 0 (default) powered up 1 powered down 6:4 ? reserved 3:2 power-down boost converter. configures the power state of the boost converter. 00 powered up 01 (default) boost mode bypass. turns the boost fet off, the re ctifying fet on, and the remaining boost circuitry in a low- power state, with vbst = vp. powers down inter nal-control circuitry when operating in vbst = vp mode. 10?11 reserved 1?reserved 0pdn_ all power down all. configures the CS35L32 power state. can be used to quickly power down the device but is not equivalent to using all of the individual power-down bits. 0 (default) powered up, as per individual controls in power control registers 1 and 2. 1 powered down. all affected blocks are powered down, r egardless of individual power-down bit settings.
ds963f5 37 CS35L32 7.6 power control 2 7.6 power control 2 address 0x07 r/w 76543210 pdn_vmon pdn_imon pdn_vpmon ? sdout_3st ? default11101000 bits name description 7pdn_ vmon power-down vmon adc. configures the power state of the adc front end and the adc used to monitor the vsense input pins to create the vmon data. 0 powered up 1 (default) powered down 6pdn_ imon power-down imon adc. configures the power state of the adc front end, and the adc, and range selection circuitry used to monitor the isense input pins to create the imon data. 0 powered up 1 (default) powered down 5pdn_ vpmon power-down vpmon adc. configures the adc front end power stat e and the adc used to monitor the vp supply pin to create the vp data. 0 powered up 1 (default) powered down 4?reserved 3 sdout_ 3st tristate the adsp sdout path. configures the hi-z state of the adsp sdout output path. 0 sdout is powered up. 1 (default) sdout is hi-z. 2:0 ? reserved 7.7 clocking control address 0x08 r/w 76543210 mclkdis mclkdiv2 ? ratio default01000000 because clock rates must be stable when the device is powered up, the device must be powered down before changing clock rates. bits name description 7 mclkdis mclk disable. configures the state of mclk int before its fan-out to all the internal circuitry. 0 (default) on 1 off. disables the clock tree to save power when the device is powered down. set only after the device powers down. 6 mclkdiv2 mclk divide by 2. configures a divide between the input pin mclk and the derived core clock, mclk int . 0 no divide 1 (default) divide by 2 5:1 ? reserved 0ratio f mclk(int)/ f lrck ratio. ta b l e 3 - 1 2 shows the effect of these sett ings on the master mode duty cycle. 0 (default)128 1 125 application: refer to section 4.11.2, ?master and slave timing.? 7.8 low battery thresholds address 0x09 r/w 76543210 ? lowbat_th[1:0] lowbat_recov[2:0] ? default00100110 bits name description 7:6 ? reserved 5:4 lowbat_ th low battery nominal threshold, falling vp. see ta b l e 3 - 3 for accuracy specifications. 00 3.1 v 01 3.2 v 10 (default) 3.3 v 11 3.4 v 3:1 lowbat_ recov low battery nominal recovery threshold, rising vp. see ta b l e 3 - 3 for accuracy specifications. 000 reserved 001 3.2 v 010 3.3 v 011 (default) 3.4 v 100 3.5 v 101 3.6 v 110?111 3.6 v 0?reserved.
38 ds963f5 CS35L32 7.9 battery voltage monitor 7.9 battery voltage monitor address 0x0a r/o 76543210 vpmon[7:0] default00000000 bits name description 7:0 vpmon battery voltage (vp) monitor. represents the vpmon (d out ) value in the equation in section 4.8.4. 1000 0000 ?128 1000 0001 ?127? 1111 1111 ?1 0000 0000 0 (default) 0000 0001 +1 0000 0010 +2 ? 0111 1111 +127 7.10 boost converter peak current protection control address 0x0b r/w 76543210 bst_ipk[7:0] default01000000 bits name description 7:0 bst_ipk boost converter peak current limit (a). configures the peak current limit on the boost converter?s output. if the amp lifier or leds attempt to draw current above this limit, only the set limit curr ent is provided and, consequently, the boost voltage droops. t he user must not write values higher than 0x80 to this register. 0000 0000 2.89 ? 0010 0000 3.30 ? 0100 0000 (default) 3.72 ? 0110 0000 4.14 ? 1000 0000 4.56 1000 0001?1111 1111 reserved 7.11 scaling address 0x0c r/w 76543210 ? imon_scale[3:0] default00000111 bits name description 7:4 ? reserved 3:0 imon_ scale select imon adc scaling. configures the scaling of data bits from the adc to be output from the adsp as the imon data word. the scale is selected from the encoded adc output data bus with bit 22 being the adc data msb. scaling control can be used to improve the reported sample resolution for low-level signals or to divide down the signal. 0000 15 down to 0 ? 0111 (default) 22 down to 7 1000 23 down to 8 1001 24 down to 9 1010 25 down to 10 1011?1111 reserved note: for 12-bit implementations, imon_scale remains the same. the msb is in the same place for 12- and 16-bit formats, 7.12 led and audio power-budget management address 0x0d r/w 7654 3 210 ? iled_mng audiogain_mng ? vboost_mng[1:0] default0000 0 010 bits name description 7:5 ? reserved 4 iled_mng led current management 0 (default) automatically reduce led current, only to avoid thermal shutdown or current limiting the boost converter. 1 user controls led current (nonautomatic). 3 audiogain_ mng audio-gain management when leds are active. 0 (default) automatically reduces audio volume once by 3 db, only if needed to avoid thermal shutdown or current limiting the boost converter. if the condition persists, the CS35L32 examines iled_mng and responds accordingly. audio recovers to original volume automatically at the end of the led event. 1 user controls audio volume (nonautomatic). 2?reserved 1:0 vboost_ mng boost voltage control. 00 automatically managed. boost-converter output voltage is the higher of the two: class g or adaptive led voltage. 01 automatically managed irrespective of audio, adapting fo r low-power dissipation when leds are on, and operating in fixed-boost bypass mode if leds are off (vbst = vp). 10 (default) boost voltage fixed in bypass mode (vbst = vp). 11 boost voltage fixed at 5 v.
ds963f5 39 CS35L32 7.13 adsp control 7.13 adsp control address 0x0f r/w 76543210 adsp_drive m/s datcnf[1:0] share ? default00100000 bits name description 7adsp_ drive adsp output drive strength. selects the drive strength used fo r the adsp outputs. these outputs include sdout as well as sclk and lrck when the device is in master mode. table 3-8 lists drive-strength specifications. 0 (default) 1x 10.5x 6 m/s adsp master/slave mode. confi gures the adsp i/o clocking. see section 4.11.2 for details . 0 (default) slave (sclk/lrck input only) 1 master (sclk/lrck output only) 5:4 datcnf data configuration for dual CS35L32 applications only. determines the data packed in a two-CS35L32 configuration. 00 left/right channels vmon[11:0], imon[11:0], vpmon[7:0]. see table 4-10 . 01 left/right channels vmon[11:0], imon[11:0], status. see table 4-11 . 10 (default) left/right channels vmon[15:0], imon [15:0]. see table 4-12 . 11 left/right channels vpmon[7:0], status. see table 4-13 . 3 share sdout sharing. determines whether one or two CS35L32 devices are on board sharing sdout. 0 (default) one ic. data configuration per table 4-9 . 1 two ics. for data configuration, refer to datcnf (bits 5:4. above). 2:0 ? reserved 7.14 class d amplifier control address 0x10 r/w 76543210 ? amp_gain[2:0] gain_chg_zc ? default00010100 bits name description 7:6 ? reserved 5:3 amp_gain amplifier gain. configures the amplifier gain. step size: ~3 db 000 mute (?80 db) 001 9 db 010 (default) 12 db 011 15 db 100 18 db 101?111 reserved 2gain_ chg_zc gain change zero-cross. configures when amp_gain (see p. 39 ) changes are applied. 0 changes are not aligned to zero crosses. 1 (default) changes are delayed to occur at zero crossings 1:0 ? reserved 7.15 protection release control address 0x11 r/w 7654 3 2 10 ? amp_short_rls ? ote_rls default 0 0 0 0 0 0 0 0 bits name description 7:3 ? reserved 2amp_ short_ rls amplifier short protection release. releases amplifier short protection that places the device into speaker-safe mode if the amplifier short condition is no longer present, which can be determined by reading amp_short (see section 7.19 ) twice. 0 (default) 1 0 ? 1 ? 0 sequence if the amplifier short condition is present, speaker-safe mode is applied. after the sequence, if the short condition is no longer present, speaker-safe mode is cleared unless an ote condition is active. during the sequence, short monitoring is inactive because the amplifier is in an off state, as explained in section 7.19 . short monitoring resumes after the sequence. 1?reserved
40 ds963f5 CS35L32 7.16 interrupt mask 1 0ote_ rls overtemperature error protection release. releases (removes) ote-caused speaker-safe mode if the ote condition is no longer present, which can be determined by reading ote (see section 7.19 ) twice. 0 (default) 1 0 ? 1 ? 0 sequence if the ote condition is present, speaker-safe mode is applied. at the end of the sequence, if the ote conditio n is no longer present, the speaker-safe mode is cleared, unless an amplifier short cause is still active. note: for these bits, if the condition that causes automatic protection becomes true again during the protection potential rele ase sequence (x_rls: 0 ? 1 ? 0), protection is not removed, the related interrupt status bi t is set again, and, if unmasked, a new interrupt is generated. 7.16 interrupt mask 1 address 0x12 r/w 765 4 3 2 1 0 ? m_adspclk_err m_mclk_err m_amp_short m_otw m_ote default 1 1 1 1 1 1 1 1 interrupt mask register bits serve as a mask for the interrupt s ources in the interrupt status registers. interrupts are descri bed in section 4.2 . bits name description 7:5 ? reserved 4 m_adspclk_err error masks 0 unmasked 1 (default) masked 3 m_mclk_err 2 m_amp_short amp_short mask 0 unmasked 1 (default) masked 1m_otwotw mask 0 unmasked 1 (default) masked 0m_oteote mask 0 unmasked 1 (default) masked 7.17 interrupt mask 2 address 0x13 r/w 76 543210 m_vmon_ovfl m_imon_ovfl m_vpmon_ovfl ? m_pdn_done default1 1 1 1111 1 interrupt mask register bits serve as a mask for the interrupt s ources in the interrupt status registers. interrupts are descri bed in section 4.2 . bits name description 7 m_vmon_ovfl overflow masks 0 unmasked 1 (default) masked 6m_imon_ovfl 5 m_vpmon_ovfl 4:1 ? reserved 0 m_pdn_done pdn_done mask 0 unmasked 1 (default) masked bits name description
ds963f5 41 CS35L32 7.18 interrupt mask 3 7.18 interrupt mask 3 address 0x14 r/w 76 5 4 3 2 1 0 m_uvlo m_led2_open m_led2_short m_led1_open m_led1_short m_lowbat m_boost_curlim m_boost_overror default 1 1 1 1 1 1 1 1 interrupt mask register bits serve as a mask for the interrupt s ources in the interrupt status registers. interrupts are descri bed in section 4.2 . registers at addresses 0x14?0x17 must not be part of a control-port autoincremented read and must be read individually. see section 4.14.1 . bits name description 7 m_uvlo uvlo mask 0 unmasked 1 (default) masked 6 m_led2_open led 2/1 open and shorted masks 0 unmasked 1 (default) masked 5 m_led2_short 4 m_led1_open 3 m_led1_short 2 m_lowbat low battery mask 0 unmasked 1 (default) masked 1 m_boost_curlim boost converter masks 0 unmasked 1 (default) masked 0 m_boost_overror 7.19 interrupt status 1 (audio) address 0x15 r/o 76543210 ? adspclk_err mclk_err amp_short otw ote default x x x x x x x x interrupt mask register bits serve as a mask for the interrupt s ources in the interrupt status registers. interrupts are descri bed in section 4.2 . registers at addresses 0x14?0x17 must not be part of a control-port autoincremented read and must be read individually. see section 4.14.1 . bits name description 7:5 ? reserved 4adspclk_ err adsp clock error. indicates that the adsp has lost synchronization. see section 4.11.2 and section 7.7 for details. 0 (default) mclk int -to-lrck ratio is valid. valid if f lrck =f mclk(int) /ratio 1mclk int -to-lrck ratio is invalid. set as the adsp resynchr onizes on initial power up and application of clocks. 3mclk_ err master clock error. indicates the mclk watchdog status. 0 (default) mclk is above ~1.25 mhz. 1 mclk is below ~1.25 mhz, so the device should be reset (reset = high ?? low), released from reset (reset = low ?? high) when a valid mclk is reapplied, and restarted. if this condition exists, the class d amplifier immediately stops switching and the outputs are internally clamped to ground . see section 4.13.3 . 2amp_ short amplifier short. indicates that either of the ampl ifier outputs (out) is driving a short circuit. 0 (default) not shorted 1 shorted. the device enters speaker-safe mode (see section 4.3.4 ). normal behavior may resume when the short condition ceases and amp_short_rls is sequenced, as described in section 7.15 . note: the circuit feeding this bit requires the amplifier to be fully powered and not in shut-down mode; if it is powered down (pdn_amp = 1) or in speaker-safe mode, the detector indica tes no short condition, even if speaker outputs are shorted. 1 otw overtemperature warning. indicates that device junc tion temperature exceeded the set limit, as described in ta b l e 3 - 3 . 0 (default) below set overtemperature warning threshold 1 above set overtemperature warning threshold 0 ote overtemperature error. indicates whether the device junction temperature exceeded the damage limit. 0 (default) below damage limit 1 above damage limit. the device enters speaker-safe mode (see section 4.3.4 ). normal behavior may resume when the ote event ends and ote_rls is sequenced, as described in section 7.15 .
42 ds963f5 CS35L32 7.20 interrupt status 2 (monitors) 7.20 interrupt status 2 (monitors) address 0x16 r/o 76543210 vmon_ovfl imon_ovfl vpmon_ovfl ? pdn_done defaultxxxxxxxx interrupt status bits are read only and sticky. interrupts are described in section 4.2 . registers at addresses 0x14?0x17 must not be part of a control-port autoincremented read and must be read individually. see section 4.14.1 . bits name description 7 vmon_ovfl xmon overflow. indicates the overrange st atus in the vmon, imon, or vpmon adc signal path 0 (default) no clipping has occurred anywhere in the adc signal path 1 clipping has occurred in the adc signal path the programming of imon_scale may cause imon_ovfl to be set. 6imon_ovfl 5 vpmon_ovfl 4:1 ? reserved 0 pdn_done power-down done. indicates whether the cs35l 32 has completely powered down and mclk can be stopped. 0 not completely powered down. pdn_done = 0 if any blocks require mclk int . after powering down using pdn_all or discrete power-down bi ts, the CS35L32 transitions to a powered-down state, after which, pdn_ done is set and mclk int can be removed. 1 (default) powered down 7.21 interrupt status 3 (le ds and boost converter) address 0x17 r/o 76 5 4 3 2 1 0 uvlo led2_open led2_short led1_open led1_s hort lowbat boost_curlim boost_overror default x x x x x x x x interrupt status bits are read only and sticky. interrupts are described in section 4.2 . registers at addresses 0x14?0x17 must not be part of a control-port autoincremented read and must be read individually. see section 4.14.1 . bits name description 7 uvlo uvlo event 0 (default) no lockout 1 uvlo detected at vp. ic shutdown. 6 led2_open led 2 open 0 (default) no open detected 1 open detected 5 led2_short led 2 shorted 0 (default) no short detected 1 short detected 4 led1_open led 1 open 0 (default) no open detected 1 open detected 3 led1_short led 1 shorted 0 (default) no short detected 1 short detected 2 lowbat battery voltage (vp) is low. this bit is updated only during an active flash led event. reads to clear this bit between any two sequential flash events are not be reflected in the status register until the next acti ve flash event is triggered. 0 (default) battery voltage normal (above lowbat_th , see section 7.8 ) 1 battery voltage low (below lowbat_recov , see section 7.8 ) 1 boost_curlim boost converter in current limit 0 (default) not in current limit 1 boost current has exceeded level programmed in bst_ipk 0 boost_ overror boost converter overvoltage error 0 (default) no overvoltage 1 overvoltage
ds963f5 43 CS35L32 7.22 led lighting status 7.22 led lighting status address 0x18 r/o 76543210 led1_flev led2_flev led1_mvev led2_mvev l ed_flen led_flinh led2_dis led_timeron defaultxxxxxxxx bits name description 7led1_ flev led1 flash event 0 (default) no driver flash current to led 1 flash current delivered to led 6led2_ flev led2 flash event 0 (default) no driver flash current to led 1 flash current delivered to led 5led1_ mvev led1 movie mode event 0 (default) no driver movie current to led 1 movie current delivered to led 4led2_ mvev led2 movie mode event 0 (default) no driver movie current to led 1 movie current delivered to led 3led_ flen flag mirroring flen 0 (default) flen low 1 flen high 2led_ flinh flag mirroring flinh 0 (default) flinh low 1 flinh high 1led2_ dis led2 disabled status reporting the use of flout2 as ad0, with no led, and tied to ground 0 (default) enabled 1 disabled (tied to ground) 0led_ timeron flash timer. flag indicating the status of the flash timer. 0 (default) timer off 1timer on 7.23 led flash mode current address 0x19 r/w 76543210 ? led_flcur[3:0] default00000000 bits name description 7:4 ? reserved 3:0 led_ flcur led flash driver current in 50-ma increments. note: if an open-circuit condition occurs on one floutx pin, the current through the other floutx pin is 50 ma lower than the led_flcur programmed value. 0000 (default) off 0001?0110 reserved 0111 350 ma 1000 400 ma 1001 450 ma 1010 500 ma 1011 550 ma 1100 600 ma 1101 650 ma 1110 700 ma 1111 750 ma
44 ds963f5 CS35L32 7.24 led movie mode current 7.24 led movie mode current address 0x1a r/w 76543210 ? led_mvcur[2:0] ? led1_mven led2_mven default00000000 bits name description 7?reserved 6:4 led_ mvcur led movie mode drive current. 000 (default) off 001 20 ma 010 40 ma 011 60 ma 100 80 ma 101 100 ma 110 120 ma 111 150 ma 3:2 ? reserved 1led1_ mven enable led 1 in movie mode 0 (default) disable led 1 1 enable led 1 0led2_ mven enable led 2 in movie mode 0 (default) disable led 2 1 enable led 2 7.25 led flash timer address 0x1b r/w 7654321 0 ? timer[4:0] timeout_mode default0010010 0 bits name description 7:6 ? reserved 5:1 timer determines the on time of the flash timer. (step size = 25 * mclk int /6 mhz ms) 0 0000 300000/mclk int s 0 0001 450000/mclk int s 0 0010 600000/mclk int s 0 0011 750000/mclk int s 0 0100 900000/mclk int s 0 0101 1050000/mclk int s 0 0110 1200000/mclk int s 0 0111 1350000/mclk int s 0 1000 1500000/mclk int s 0 1001 1650000/mclk int s 0 1010 1800000/mclk int s 0 1011 1950000/mclk int s 0 1100 2100000/mclk int s 0 1101 2250000/mclk int s 0 1110 2400000/mclk int s 0 1111 2550000/mclk int s 1 0000 2700000/mclk int s 0 0001 2850000/mclk int s 1 0010 3000000/mclk int s (default) 1 0011?1 11113000000/mclk int s 0timeout_ mode flash timeout mode 0 (default) flash timer (timeron) determines end of flash irrespective of the flen input pin. 1 end of flash determined by either flen going low or flash timer timing out. 7.26 led flash inhibit current address 0x1c r/w 76543210 ? led_flinhcur[3:0] default00000000 bits name description 7:4 ? reserved 3:0 led_ flinhcur led flash driver current in 50-ma increments. 0000 (default) off 0001 50 ma? 0010 100 ma 0011 150 ma 0100 200 ma 0101 250 ma 0110 300 ma 0111 350 ma 1000?1111 reserved
ds963f5 45 CS35L32 8 typical performance plots 8 typical performance plots 8.1 system-level efficiency and power-consumption plots for all system-level efficiency and power-consump tion plots, a simula ted speaker load (8 ?? + 33 ? h) is used; the amplifier pwm outputs (out) contain no emi filtering. efficiency calculations are ba sed on rms power delivered to the load at the generated frequency and include pow er consumption of both va and vp. figure 8-1. efficiency vs. output power?vbst = vp (vp = 3.0 v, vp = 3.6 v, vp = 4.2 v) figure 8-2. vp supply current vs. output power?vbst = vp (vp = 3.0 v, vp = 3.6 v, vp = 4.2 v) figure 8-3. efficiency vs. output power?vbst = 5.0 v (vp = 3.0 v, vp = 3.6 v, vp = 4.2 v) figure 8-4. vp supply current vs. output power?vbst = 5.0 v (vp = 3.0 v, vp = 3.6 v, vp = 4.2 v) vbst = vp, vp = 3.0 v vbst = vp, vp = 3.6 v vbst = vp, vp = 4.2 v 0 200 400 600 800 1000 1200 0 10 20 30 40 50 60 70 80 90 100 output power (mw) efficiency (%) vbst = vp, vp = 3.0 v vbst = vp, vp = 3.6 v vbst = vp, vp = 4.2 v 0 200 400 600 800 1000 1200 0 50 100 150 200 250 300 350 output power (mw) vp current (ma) vbst = 5 v, vp = 3.0 v vbst = 5 v, vp = 3.6 v vbst = 5 v, vp = 4.2 v 0 200 400 600 800 1000 1200 1400 1600 1800 200 0 0 10 20 30 40 50 60 70 80 90 100 output power (mw) efficiency (%) vbst = 5 v, vp = 3.0 v vbst = 5 v, vp = 3.6 v vbst = 5 v, vp = 4.2 v 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 100 200 300 400 500 600 700 800 900 output power (mw) vp current (ma)
46 ds963f5 CS35L32 8.2 audio output typical performance plots 8.2 audio output typical performance plots to avoid nonlinearities (distortion) introduced by the amplif ier load inductor itself, all amp lifier typical performance plots use a resistor and not a simulated speaker load. no emi filtering is populated on the amplifier outputs (out). figure 8-5. device idle power consumption, current vs. vp? vbst = 5.0 v, vbst = vp = 3.6 v figure 8-6. device idle power consumption, power vs. vp? vbst = 5.0 v, vbst = vp = 3.6 v figure 8-7. thd+n ratio vs. output power @ 1 khz, 8 ? ? bypass mode (vbst = vp = 3.6 v), fixed boost mode (vbs t = 5 v), automatic mode figure 8-8. thd+n ratio vs. frequency, 8 ? ? bypass mode (vbst = vp = 3.6 v, load = 0.5 w), fixed boost mode (vbst = 5 v, load = 1 w) 2.5 3 3.5 4 4.5 5 5.5 0 5 10 15 20 25 30 35 40 vp voltage (v) vp idle current (ma) 2.5 3 3.5 4 4.5 5 5.5 0 20 40 60 80 100 120 140 160 vp voltage (v) vp idle power (mw) vbst = vp vbst = 5 v automatic mode 0.01 0.1 1 0.001 0.01 0.1 1 10 output power (w) thd+n ratio (%) vbst = vp vbst = 5 v 100 1000 10000 0.0001 0.001 0.01 0.1 1 10 frequency (hz) thd+n ratio (%)
ds963f5 47 CS35L32 8.3 monitoring typical performance plots 8.3 monitoring typical performance plots unless otherwise noted, a ll vmon/imon plots use the amplifier as the sign al source and all measurements were taken using an 8 ? + 33 ? h load. all listed load inductances include any measured inductances contained in the connection to the load. no emi filtering is populated on the amplifier outputs (out). figure 8-9. frequency response @ 1 w? fixed-boost mode (vbst = 5 v, refer to amplitude @ 1 khz) figure 8-10. vp psrr vs. frequency, vp_ac = 100 mvpk? bypass mode (vbst = vp), fixed-boost mode (vbst = 5 v) figure 8-11. imon thd+n ratio vs. amplifier output power @ 1 khz?bypass mode (vbst = vp = 3.6 v, load = 0.5 w) fixed boost mode (vbst = 5 v, load = 1 w) figure 8-12. vmon thd+n ratio vs. amplifier output power @ 1 khz?bypass mode (vbst = vp = 3.6 v, load = 0.5 w) fixed boost mode (vbst = 5 v, load = 1 w) 100 1000 10000 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1 frequency (hz) amplitude (dbr) 100 1000 10000 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 frequency (hz) psrr (db) vbst = 5 v vbst = vp 0.001 0.01 0.1 1 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 output power (w) thd+n (db) vbst = 5 v vbst = vp 0.001 0.01 0.1 1 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 output power (w) thd+n (db)
48 ds963f5 CS35L32 8.3 monitoring typical performance plots figure 8-13. imon thd+n ratio vs. frequency? bypass mode (vbst = vp = 3.6 v, load = 0.5 w) fixed boost mode (vbst = 5 v, load = 1 w) figure 8-14. vmon thd+n ratio vs. frequency? bypass mode (vbst = vp = 3.6 v, load = 0.5 w) fixed boost mode (vbst = 5 v, load = 1 w) figure 8-15. imon frequency response @ 1 w? fixed-boost mode (vbst = 5 v) figure 8-16. vmon frequency response @ 1 w? fixed-boost mode (vbst = 5 v) 9%67 9 9%67 93 )uhtxhqf\+] 7+'1g% 9%67 9 9%67 93 )uhtxhqf\+] 7+'1g% 8? , 4.7? h load 8? , 10? h load 8? , 15? h load 8? , 33? h load 100 1000 10000 ?1.5 ?1 ?0.5 0 0.5 1 1.5 frequency (hz) amplitude (dbr) +/rdg +/rdg +/rdg +/rdg )uhtxhqf\+] $psolwxghg%u
ds963f5 49 CS35L32 9 parameter definitions 9 parameter definitions figure 8-17. vmon to imon phase vs. frequency @ 1 w? fixed-boost mode (vbst = 5 v) load = 8 ? + 5 ? h, 8 ? + 10 ? h, 8 ? + 33 ? h, 8 ? + 15 ? h 1 figure 8-18. imon fft, 1 khz @ load = 0.9 w?vbst = 5 v figure 8-19. imon fft, 1 khz @ no load?vbst = 5 v mclk int . internal clock that is either equal to the signal connected to the mclk (mclk ext ) or is equal to mclk ext /2, depending on the setting of the mclk divide-by-2 control (mclkdiv2), described in section 7.7 . output offset voltage. describes the dc offset voltage present at the amplifier?s output when its input signal is in a mute state. the offset exists due to cmos process limitat ions and is proportional to analog volume settings. when measuring the offset out of the line amplifier, the line am plifier is on and the headphone amplifier is off; when measuring the offset out of the headphone amplifier, the headphone amplifier is on and the line amplifier is off. signal-to-noise ratio (snr). the ratio of the rms value of the output signal, where p out is equivalent to the specified output power at thd+n < 1%, to the rms value of the noise floor with no input signal applied and measured over the specified bandwidth, ty pically 20 hz to 20 khz. this measurem ent technique has been accepted by the electronic industries association of ja pan, eiaj cp?307. expressed in decibels. total harmonic distortion + noise (thd+n). the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typic ally 10 hz to 20 khz), including distortion components. thd+n is measured at ?1 and ?20 dbfs for the analog in put and 0 and ?20 db for the analog output as suggested in aes17?1991 annex a. thd+n is expressed in decibel units. 8? , 4.7? h load 8? , 10? h load 8? , 15? h load 8? , 33? h load 100 1000 10000 ?30 ?20 ?10 0 10 20 30 frequency (hz) phase (deg) 100 1000 10000 ?140 ?120 ?100 ?80 ?60 ?40 ?20 frequency (hz) amplitude (dbfs) 100 1000 10000 ?140 ?120 ?100 ?80 ?60 ?40 ?20 frequency (hz) amplitude (dbfs)
50 ds963f5 CS35L32 10 package dimensions 10 package dimensions figure 10-1. 30-ball wlcsp package drawing 11 thermal characteristics table 11-1. thermal resistance parameters symbol min typical max units junction-to-ambient thermal impedance ? ja ?50?c/watt e wafer back side side view ball a1 location indicator x y a a2 a1 bump side e n m c d ball a1 location indicator b seating plane x z y a3 notes: ? dimensioning and tolerances per asme y 14.5m?1994. ? the ball a1 position indicator is for illustration purposes only and may not be to scale.7 ? dimension ?b? applies to the solder sphere diameter and is measured at the midpoint between the package body and the seating p lane datum z. ? dimension a3 describes the thickness of the backside film. table 10-1. wlcsp package dimensions dimension millimeters minimum nominal maximum a 0.451 0.494 0.537 a1 0.169 0.194 0.219 a2 0.275 0.3 0.325 a3 0.022 0.025 0.028 m bsc 2.000 bsc n bsc 1.600 bsc b 0.243 0.268 0.293 c ref 0.264 ref d ref 0.295 ref e bsc 0.400 bsc x 2.560 2.590 2.620 y 2.108 2.138 2.168 ccc = 0.10 ddd = 0.05 note: controlling dim ension is millimeters. ?b ?ddd z x y ?ccc z
ds963f5 51 CS35L32 12 ordering information 12 ordering information 13 references 1. nxp semiconductors (founded by philips semiconductor), the i2c-bus specification and user manual . um10204 rev. 03, june 19, 2007 http://www.nxp.com 14 revision history table 12-1. ordering information product description package halogen free pb free grade temperature range container order number CS35L32 boosted class d amplifier with speaker-protection monitoring and flash led drivers 30-ball wlcsp yes yes commercial ?10c to 70c tape and reel CS35L32-cwzr table 14-1. revision history date changes f2 mar ?14 ? updated values for boost fet peak-current limit in table 3-4 . f3 may ?14 ? updated the maximum value for vbst in table 3-4 . f4 jul ?14 ? updated package dimensions in table 10-1 . f5 aug ?15 ? updated package dimensions in table 10-1 and package drawing to include backside film. ? updated legal disclaimer. contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com . important notice the products and services of cirrus logic international (uk) limited; cirrus logic, inc.; and other companies in the cirrus log ic group (collectively either ?cirrus logic? or ?cirrus?) are sold subject to cirrus logic?s terms and conditions of sale supplied at the time of order acknowledgmen t, including those pertaining to warranty, indemnification, and limitation of liability. software is provided pursuant to applicable license terms. cirrus logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain t he latest version of relevant information from cirrus logic to verify that the information is current and complete. testing and other quality control techniq ues are utilized to the extent cirrus logic deems necessary. specific testing of all parameters of each device is not necessarily performed. in order to minimize ris ks associated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. cirrus logic is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of cirrus logi c products. certain applications using semiconductor products may involve pote ntial risks of death, personal injury, or severe property or environmental damage (?critical applicati ons?). cirrus logic products are not design ed, authorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, nuclear systems, life support products or other critical applications. incl usion of cirrus logic products in such applications is understood to be fully at the customer? s risk and cirrus logic disclaim s and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for part icular purpose, with regard to any cirrus logic product that is used in such a manner. if t he customer or customer?s customer uses or permits the use of ci rrus logic products in critical applications, customer agrees, by such use, to fully indemnify cirrus logic, its officers, directors, employees, distri butors and other agents from any and all liability, including attorneys? fees and costs, that may result from or arise in co nnection with these uses. this document is the property of cirrus logic and by furnishing this information, cirrus logic grants no license, express or im plied, under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. any provision or publication of any t hird party?s products or services does not constitute cirrus logic?s approval, license, warranty or endorsement thereof. cirrus logic gives consent for copies to be m ade of the information contained herein only for use within your organization with respect to cirrus logic integrated circuits or other products of cirrus logic , and only if the reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice) . this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resal e. this document and its information is provided ?as is? without warranty of any kind (express or implied). all statutory warranties and conditions are excluded to the fullest extent possible. no responsibility is assumed by cirrus logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. cirrus logic, cirrus, the cirrus logic logo design, and soundclea r are among the trademarks of cirrus logic. other brand and product names may be trademarks or service marks of their respective owners. copyright ? 2012?2015 cirrus logic, inc. all rights reserved.

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